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1. 发明授权

US08462534B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08462534B2
公开(公告)日：2013-06-11
申请号：US13430860
申请日：2012-03-27
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

2. 发明授权

US08159853B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08159853B2
公开(公告)日：2012-04-17
申请号：US12693010
申请日：2010-01-25
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

3. 发明授权

US08576637B2 Memory module including memory buffer and memory system having the same 有权
标题翻译：内存模块包括内存缓冲区和具有相同内存的系统
公开(公告)号：US08576637B2
公开(公告)日：2013-11-05
申请号：US12959504
申请日：2010-12-03
申请人： Soon-Deok Jang , Seok-Il Kim , Seung-Jin Seo , You-Keun Han
发明人： Soon-Deok Jang , Seok-Il Kim , Seung-Jin Seo , You-Keun Han
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.
摘要翻译：公开了一种在并行测试模式和模式寄存器控制模式之间选择的存储器缓冲器，以及具有存储器缓冲器的存储器模块和存储器系统。存储器缓冲器包括控制电路和模式选择电路。控制电路基于第一芯片选择信号，第二芯片选择信号，行地址信号，列地址信号和写使能信号来生成模式控制信号。模式选择电路响应于模式控制信号选择并行测试模式和模式寄存器控制模式中的一种。

4. 发明授权

US07965530B2 Memory modules and memory systems having the same 有权
标题翻译：存储器模块和具有相同功能的存储器系统
公开(公告)号：US07965530B2
公开(公告)日：2011-06-21
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
发明人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

5. 发明申请

US20110176371A1 MEMORY MODULE INCLUDING MEMORY BUFFER AND MEMORY SYSTEM HAVING THE SAME 有权
标题翻译：包含存储器缓冲器的存储器模块和具有该存储器模块的存储器系统
公开(公告)号：US20110176371A1
公开(公告)日：2011-07-21
申请号：US12959504
申请日：2010-12-03
申请人： Soon-Deok Jang , Seok-Il Kim , Seung-Jin Seo , You-Keun Han
发明人： Soon-Deok Jang , Seok-Il Kim , Seung-Jin Seo , You-Keun Han
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.
摘要翻译：公开了一种在并行测试模式和模式寄存器控制模式之间选择的存储器缓冲器，以及具有存储器缓冲器的存储器模块和存储器系统。存储器缓冲器包括控制电路和模式选择电路。控制电路基于第一芯片选择信号，第二芯片选择信号，行地址信号，列地址信号和写使能信号来生成模式控制信号。模式选择电路响应于模式控制信号选择并行测试模式和模式寄存器控制模式中的一种。

6. 发明申请

US20120239903A1 ADDRESS TRANSFORMING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：地址变换电路和包括其的半导体存储器件
公开(公告)号：US20120239903A1
公开(公告)日：2012-09-20
申请号：US13343803
申请日：2012-01-05
申请人： Seok-Il Kim , You-Keun Han , Sung-Ho Choi
发明人： Seok-Il Kim , You-Keun Han , Sung-Ho Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G11C8/04 , G11C8/06
摘要： An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.
摘要翻译：一种在系统引导时能够改变存储器映射的地址变换电路包括开关控制信号发生电路和地址变换单元。开关控制信号发生电路产生与复位信号同步的交替使能的开关控制信号。地址变换单元响应于开关控制信号，变换第一地址的位以产生第二地址。因此，包括地址变换电路的半导体存储器件具有长寿命和高可靠性。

7. 发明申请

US20110115509A1 Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices 有权
标题翻译：包括用于测试能力的设计的半导体器件和包括这些器件的半导体模块和测试系统
公开(公告)号：US20110115509A1
公开(公告)日：2011-05-19
申请号：US12915314
申请日：2010-10-29
申请人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
发明人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
IPC分类号： G01R31/3187
CPC分类号： G01R31/31717 , G01R31/2884 , G01R31/3004 , G01R31/3185 , H01L22/34
摘要： A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.
摘要翻译：半导体器件包括电阻器端子，参考电压发生器和检测器。电阻端子连接到外部电阻。参考电压发生器产生至少一个参考电压。检测器至少部分地基于电阻器端子电压和至少一个参考电压产生检测信号。检测信号表示与电阻端子的电连接的状态。电阻端子电压是电阻端子处的电压。

8. 发明授权

US09128817B2 Address transforming circuit and semiconductor memory device including the same 有权
标题翻译：地址变换电路和包括其的半导体存储器件
公开(公告)号：US09128817B2
公开(公告)日：2015-09-08
申请号：US13343803
申请日：2012-01-05
申请人： Seok-Il Kim , You-Keun Han , Sung-Ho Choi
发明人： Seok-Il Kim , You-Keun Han , Sung-Ho Choi
IPC分类号： G11C8/04 , G06F12/02 , G11C8/06
CPC分类号： G06F12/0207 , G11C8/04 , G11C8/06
摘要： An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.
摘要翻译：一种在系统引导时能够改变存储器映射的地址变换电路包括开关控制信号发生电路和地址变换单元。开关控制信号发生电路产生与复位信号同步的交替使能的开关控制信号。地址变换单元响应于开关控制信号，变换第一地址的位以产生第二地址。因此，包括地址变换电路的半导体存储器件具有长寿命和高可靠性。

9. 发明申请

US20070171740A1 Semiconductor memory module and semiconductor memory device 有权
标题翻译：半导体存储器模块和半导体存储器件
公开(公告)号：US20070171740A1
公开(公告)日：2007-07-26
申请号：US11540607
申请日：2006-10-02
申请人： Seok-Il Kim , You-Keun Han , Hoe-Ju Chung , Young-Man Ahn
发明人： Seok-Il Kim , You-Keun Han , Hoe-Ju Chung , Young-Man Ahn
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/025 , H05K1/0268 , H05K1/181
摘要： A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.
摘要翻译：公开了半导体存储器模块和半导体存储器件。在一个实施例中，本发明提供了一种半导体存储器模块，包括电路板，多个半导体存储器件，适于在测试模式和正常操作模式下操作并安装在电路板上，第一信号线组包括多个连接到多个半导体存储器件的第一信号线，以及多个第二信号线组。每个半导体存储器件包括适于从第一信号线接收第一信号的第一端子，连接到第二信号线组中对应的一个信号线组的第二端子，适于在测试模式期间接收使能信号的第三端子和信号传输该单元适于响应于使能信号将第二信号输出到第二终端。

10. 发明授权

US08742780B2 Semiconductor devices including design for test capabilities and semiconductor modules and test systems including such devices 有权
标题翻译：半导体器件包括测试能力设计和半导体模块以及测试系统，包括这些器件
公开(公告)号：US08742780B2
公开(公告)日：2014-06-03
申请号：US12915314
申请日：2010-10-29
申请人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
发明人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
IPC分类号： G01R31/3187 , G01R31/317 , G01R31/3185 , G01R31/28 , G01R31/30 , H01L21/66
CPC分类号： G01R31/31717 , G01R31/2884 , G01R31/3004 , G01R31/3185 , H01L22/34
摘要： A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.
摘要翻译：半导体器件包括电阻器端子，参考电压发生器和检测器。电阻端子连接到外部电阻。参考电压发生器产生至少一个参考电压。检测器至少部分地基于电阻器端子电压和至少一个参考电压产生检测信号。检测信号表示与电阻端子的电连接的状态。电阻端子电压是电阻端子处的电压。

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