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1. 发明授权

US07965530B2 Memory modules and memory systems having the same 有权
标题翻译：存储器模块和具有相同功能的存储器系统
公开(公告)号：US07965530B2
公开(公告)日：2011-06-21
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
发明人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

2. 发明授权

US08108741B2 Semiconductor memory device having mount test circuits and mount test method thereof 失效
标题翻译：具有安装测试电路及其安装测试方法的半导体存储器件
公开(公告)号：US08108741B2
公开(公告)日：2012-01-31
申请号：US12219815
申请日：2008-07-29
申请人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
发明人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/28 , G11C29/40 , G11C2029/4002
摘要： A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.
摘要翻译：提供一种具有安装测试电路及其安装测试方法的半导体存储器件。用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径发生。

3. 发明申请

US20090037784A1 Semiconductor memory device having mount test circuits and mount test method thereof 失效
标题翻译：具有安装测试电路及其安装测试方法的半导体存储器件
公开(公告)号：US20090037784A1
公开(公告)日：2009-02-05
申请号：US12219815
申请日：2008-07-29
申请人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
发明人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
IPC分类号： G11C29/08 , G06F11/00
CPC分类号： G11C29/28 , G11C29/40 , G11C2029/4002
摘要： A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.
摘要翻译：提供一种具有安装测试电路及其安装测试方法的半导体存储器件。用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径发生。

4. 发明申请

US20130039142A1 INPUT BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：输入缓存器电路，半导体存储器件和存储器系统
公开(公告)号：US20130039142A1
公开(公告)日：2013-02-14
申请号：US13654723
申请日：2012-10-18
申请人： Hyoung-Seok Kim , Kwan-Yong Jin
发明人： Hyoung-Seok Kim , Kwan-Yong Jin
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C7/22 , G11C7/225 , G11C8/06
摘要： An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
摘要翻译：输入缓冲电路包括逻辑单元，时钟使能缓冲器和时钟缓冲器。逻辑单元被配置为接收时钟信号和时钟使能信号，并且输出指示时钟信号是否正常输入的判定信号，其中当正常输入时钟信号时，决定信号被激活。响应于决定信号的激活，时钟使能缓冲器被配置为缓冲时钟使能信号并激活内部时钟使能信号。响应于内部时钟使能信号的激活，时钟缓冲器被配置为缓冲时钟信号并输出内部时钟信号。

5. 发明授权

US08531910B2 Input buffer circuit, semiconductor memory device and memory system 有权
标题翻译：输入缓冲电路，半导体存储器件和存储器系统
公开(公告)号：US08531910B2
公开(公告)日：2013-09-10
申请号：US13654723
申请日：2012-10-18
申请人： Hyoung-Seok Kim , Kwan-Yong Jin
发明人： Hyoung-Seok Kim , Kwan-Yong Jin
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/22 , G11C7/225 , G11C8/06
摘要： An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
摘要翻译：输入缓冲电路包括逻辑单元，时钟使能缓冲器和时钟缓冲器。逻辑单元被配置为接收时钟信号和时钟使能信号，并且输出指示时钟信号是否正常输入的判定信号，其中当正常输入时钟信号时，决定信号被激活。响应于决定信号的激活，时钟使能缓冲器被配置为缓冲时钟使能信号并激活内部时钟使能信号。响应于内部时钟使能信号的激活，时钟缓冲器被配置为缓冲时钟信号并输出内部时钟信号。

6. 发明授权

US08295122B2 Input buffer circuit, semiconductor memory device and memory system 有权
标题翻译：输入缓冲电路，半导体存储器件和存储器系统
公开(公告)号：US08295122B2
公开(公告)日：2012-10-23
申请号：US12851718
申请日：2010-08-06
申请人： Hyoung-Seok Kim , Kwan-Yong Jin
发明人： Hyoung-Seok Kim , Kwan-Yong Jin
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/22 , G11C7/225 , G11C8/06
摘要： An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
摘要翻译：输入缓冲电路包括逻辑单元，时钟使能缓冲器和时钟缓冲器。逻辑单元被配置为接收时钟信号和时钟使能信号，并且输出指示时钟信号是否正常输入的判定信号，其中当正常输入时钟信号时，决定信号被激活。响应于决定信号的激活，时钟使能缓冲器被配置为缓冲时钟使能信号并激活内部时钟使能信号。响应于内部时钟使能信号的激活，时钟缓冲器被配置为缓冲时钟信号并输出内部时钟信号。

7. 发明申请

US20110032787A1 INPUT BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：输入缓存器电路，半导体存储器件和存储器系统
公开(公告)号：US20110032787A1
公开(公告)日：2011-02-10
申请号：US12851718
申请日：2010-08-06
申请人： Hyoung-Seok Kim , Kwan-Yong Jin
发明人： Hyoung-Seok Kim , Kwan-Yong Jin
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C7/22 , G11C7/225 , G11C8/06
摘要： An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.
摘要翻译：输入缓冲电路包括逻辑单元，时钟使能缓冲器和时钟缓冲器。逻辑单元被配置为接收时钟信号和时钟使能信号，并且输出指示时钟信号是否正常输入的判定信号，其中当正常输入时钟信号时，决定信号被激活。响应于决定信号的激活，时钟使能缓冲器被配置为缓冲时钟使能信号并激活内部时钟使能信号。响应于内部时钟使能信号的激活，时钟缓冲器被配置为缓冲时钟信号并输出内部时钟信号。

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