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1. 发明授权

US08358546B2 Semiconductor device having additive latency 有权
标题翻译：具有附加延迟的半导体器件
公开(公告)号：US08358546B2
公开(公告)日：2013-01-22
申请号：US12945521
申请日：2010-11-12
申请人： Yang-ki Kim , Jung-hwan Choi
发明人： Yang-ki Kim , Jung-hwan Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.
摘要翻译：半导体器件接收对应于存储器访问操作的命令，并在附加等待时间之后执行存储器存取操作。当接收到命令时，加法等待时间开始。该半导体器件包括用于控制时钟信号的相位并输出相位控制的时钟信号的相位控制器，以及用于产生和输出控制信号的控制器，用于使得能够在加法器中的预定时间禁用相位控制器潜伏期

2. 发明授权

US08203860B2 Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads 有权
标题翻译：半导体存储器件具有用于补偿数据输入 - 输出焊盘的寄生电阻的驱动器
公开(公告)号：US08203860B2
公开(公告)日：2012-06-19
申请号：US12461141
申请日：2009-08-03
申请人： Hae-young Chung , Yang-ki Kim , Seok-woo Choi
发明人： Hae-young Chung , Yang-ki Kim , Seok-woo Choi
IPC分类号： G11C5/06 , H01S4/00 , G11C8/08
CPC分类号： G11C5/063 , G11C8/08 , Y10T29/49002
摘要： A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.
摘要翻译：一种半导体存储器件，包括电源电压焊盘，接地电压焊盘以及布置在电源电压焊盘和接地电压焊盘之间的至少两个数据输入/输出焊盘。半导体存储器件具有第一上拉驱动器，其连接到位于与电源电压焊盘相距第一距离处的第二数据输入/输出焊盘，以及第一下拉驱动器，其连接到第一数据输入/输出焊盘位于离地电压焊盘的第二距离处。

3. 发明申请

US20110115509A1 Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices 有权
标题翻译：包括用于测试能力的设计的半导体器件和包括这些器件的半导体模块和测试系统
公开(公告)号：US20110115509A1
公开(公告)日：2011-05-19
申请号：US12915314
申请日：2010-10-29
申请人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
发明人： Seok-Il Kim , Ho-Suk Lee , You-Keun Han , Yang-Ki Kim
IPC分类号： G01R31/3187
CPC分类号： G01R31/31717 , G01R31/2884 , G01R31/3004 , G01R31/3185 , H01L22/34
摘要： A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.
摘要翻译：半导体器件包括电阻器端子，参考电压发生器和检测器。电阻端子连接到外部电阻。参考电压发生器产生至少一个参考电压。检测器至少部分地基于电阻器端子电压和至少一个参考电压产生检测信号。检测信号表示与电阻端子的电连接的状态。电阻端子电压是电阻端子处的电压。

4. 发明申请

US20110025373A1 Semiconductor devices having ZQ calibration circuits and calibration methods thereof 有权
公开(公告)号：US20110025373A1
公开(公告)日：2011-02-03
申请号：US12656587
申请日：2010-02-04
申请人： Jun-bae Kim , Yang-ki Kim
发明人： Jun-bae Kim , Yang-ki Kim
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , G11C7/02 , G11C7/04 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure.

5. 发明申请

US20100259294A1 ON-DIE TERMINATION LATENCY CLOCK CONTROL CIRCUIT AND METHOD OF CONTROLLING THE ON-DIE TERMINATION LATENCY CLOCK 有权
标题翻译：电子终端终止时钟控制电路及控制终端终止时钟的方法
公开(公告)号：US20100259294A1
公开(公告)日：2010-10-14
申请号：US12754043
申请日：2010-04-05
申请人： Chul-hwan CHOO , Jun-bae Kim , Yang-ki Kim , Jun-ho Shin
发明人： Chul-hwan CHOO , Jun-bae Kim , Yang-ki Kim , Jun-ho Shin
IPC分类号： H03K19/003
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272
摘要： A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.
摘要翻译：半导体器件包括片上终端（ODT）等待时钟控制电路和由ODT等待时钟控制电路控制的ODT电路。 ODT等待时钟控制电路包括ODT使能信号发生器，其接收通过ODT电路的ODT焊盘输入的ODT信号，并产生ODT使能信号;以及ODT等待时钟发生器，响应于所述ODT等待时间产生多个ODT等待时间 ODT使能信号。 ODT使能信号包括第一逻辑电平的使能周期和第二和不同逻辑电平的禁用周期，并且ODT使能信号发生器通过将使能周期的宽度增加预定时钟周期来产生ODT使能信号，并且只在增加的使能期间产生时钟。

6. 发明申请

US20080042690A1 DATA RECEIVING APPARATUS USING SEMI-DUAL REFERENCE VOLTAGE 有权
标题翻译：使用双参考电压的数据接收装置
公开(公告)号：US20080042690A1
公开(公告)日：2008-02-21
申请号：US11747685
申请日：2007-05-11
申请人： Yang-ki Kim , Young-jin Jeon
发明人： Yang-ki Kim , Young-jin Jeon
IPC分类号： G01R25/00
CPC分类号： H04L25/0292
摘要： A semi-dual reference voltage data receiving apparatus includes a first input buffer, a second input buffer, and a phase detector wherein the first input buffer includes a first input receiving unit, a first sense amplifier, and a first current offset controlling unit. The first sense amplifier senses and amplifies the voltage difference between the voltage of a first terminal of a first input transistor and the voltage of a first terminal of a second input transistor. The first current offset controlling unit controls the offset of the current that flows through the second terminal of the second input transistor.
摘要翻译：半双参考电压数据接收装置包括第一输入缓冲器，第二输入缓冲器和相位检测器，其中第一输入缓冲器包括第一输入接收单元，第一读出放大器和第一电流偏移控制单元。第一读出放大器感测并放大第一输入晶体管的第一端子的电压与第二输入晶体管的第一端子的电压之间的电压差。第一电流偏移控制单元控制流过第二输入晶体管的第二端子的电流的偏移。

7. 发明申请

US20070132494A1 Duty cycle correction amplification circuit 有权
标题翻译：占空比校正放大电路
公开(公告)号：US20070132494A1
公开(公告)日：2007-06-14
申请号：US11527381
申请日：2006-09-27
申请人： Yang Ki Kim
发明人： Yang Ki Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/023
摘要： A duty cycle correction amplification circuit is disclosed and comprises a first amplifier comprising dual first MOS differential input transistors gated respectively by first and second reference signals, and adapted to generate first and second preliminary signals, a second amplifier comprising dual second MOS differential input transistors respectively gated by first and second preliminary signals and adapted to generate first and second internal signals, and a duty cycle corrector adapted to correct a duty cycle associated with the first and second internal signals, wherein one of the first and second internal signals comprises an amplified output signal having a corrected duty cycle.
摘要翻译：公开了一种占空比校正放大电路，包括分别由第一和第二参考信号门控的第一和第二MOS差分输入晶体管的第一放大器，并且适于产生第一和第二预备信号，第二放大器分别包括双第二MOS差分输入晶体管由第一和第二初步信号门控并适于产生第一和第二内部信号，以及占空比校正器，其适于校正与第一和第二内部信号相关联的占空比，其中第一和第二内部信号之一包括放大的输出信号具有校正的占空比。

8. 发明授权

US08373475B2 Phase interpolator and delay locked-loop circuit 有权
标题翻译：相位内插器和延迟锁相环电路
公开(公告)号：US08373475B2
公开(公告)日：2013-02-12
申请号：US13270509
申请日：2011-10-11
申请人： Tae-Sik Na , Yang-Ki Kim
发明人： Tae-Sik Na , Yang-Ki Kim
IPC分类号： H03L7/06
CPC分类号： H03H11/16 , H03L7/0818
摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.
摘要翻译：相位插值器包括延迟差检测器和相位插值驱动器。延迟差检测器接收延迟码以检测延迟差。相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

9. 发明申请

US20120086486A1 PHASE INTERPOLATOR AND DELAY LOCKED-LOOP CIRCUIT 有权
标题翻译：相位插补器和延迟锁定环路
公开(公告)号：US20120086486A1
公开(公告)日：2012-04-12
申请号：US13270509
申请日：2011-10-11
申请人： Tae-Sik NA , Yang-Ki Kim
发明人： Tae-Sik NA , Yang-Ki Kim
IPC分类号： H03L7/08 , H03H11/16
CPC分类号： H03H11/16 , H03L7/0818
摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.
摘要翻译：相位插值器包括延迟差检测器和相位插值驱动器。延迟差检测器接收延迟码以检测延迟差。相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

10. 发明授权

US08049545B2 Delay-locked loop circuit controlled by column strobe write latency 失效
标题翻译：延迟锁定环路电路由列选通写入延迟控制
公开(公告)号：US08049545B2
公开(公告)日：2011-11-01
申请号：US12644044
申请日：2009-12-22
申请人： Yang-ki Kim , Seok-hun Hyun
发明人： Yang-ki Kim , Seok-hun Hyun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/1565 , H03K2005/00026 , H03K2005/0011 , H03K2005/00202 , H03K2005/00208
摘要： The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.
摘要翻译： DLL电路包括根据外部输入的列地址选通写入延迟（CWL）信号来控制单位延迟电路的偏置电流的控制电路，和/或DCC控制电路，其调节DCC的DCC电流的步长，根据外部输入列地址选通写入延迟（CWL）信号。 CWL信号可以由半导体存储器件输入，并且可以指示列地址选通写入半导体存储器件的延迟。半导体存储器件可以是双倍数据速率（DDR）同步DRAM（SDRAM）器件。

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