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1. 发明授权

US07965530B2 Memory modules and memory systems having the same 有权
标题翻译：存储器模块和具有相同功能的存储器系统
公开(公告)号：US07965530B2
公开(公告)日：2011-06-21
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
发明人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

2. 发明授权

US08819790B2 Cooperation method and system between send mechanism and IPSec protocol in IPV6 environment 有权
标题翻译： IPV6环境下的发送机制与IPSec协议的协作方法和系统
公开(公告)号：US08819790B2
公开(公告)日：2014-08-26
申请号：US12040355
申请日：2008-02-29
申请人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
发明人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
IPC分类号： H04L9/32 , G06F21/00 , H04L29/06
CPC分类号： H04L63/164
摘要： The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec. The present invention allows the authentication information shared between SEND and IPSec in a mobile environment, where the network is frequently accessed, enabling IPSec secure communication at a lower cost.
摘要翻译：本发明涉及在IPv6环境中体现SEND与IPSec之间的协作系统的方法。根据本发明的SEND和IPSec之间的协作系统包括：接收认证完成报告消息，该消息包括通过SEND完成认证的主机的第一IP地址; 生成与所述主机对应的新认证信息，并将所述新认证信息存储在临时存储区域中，如果所述主机的认证信息不存在于所述临时存储区域中，则所述认证信息包括所述第一IP地址; 并且如果从IPSec接收到包含第二IP地址的认证检查请求消息，则检查该临时存储区域中是否存在第二IP地址，并向IPSec发送检查结果。本发明允许在经常访问网络的移动环境中在SEND和IPSec之间共享的认证信息以更低的成本实现IPSec安全通信。

3. 发明授权

US08661276B2 Apparatus and method for power control of a central processing unit in a multi-core system 有权
标题翻译：多核系统中央处理单元的功率控制装置及方法
公开(公告)号：US08661276B2
公开(公告)日：2014-02-25
申请号：US12909417
申请日：2010-10-21
申请人： Ji-Hwan Park , Hyun-Moo Kim , Nam-Su Ha , Jung-Hwan Choi , Jin-Hyo Kim , Tae-Il Kim , Il-Hyun Cho , Sung-Joon Jang , Hye-Sun Kim , Jin-Kyoung Du
发明人： Ji-Hwan Park , Hyun-Moo Kim , Nam-Su Ha , Jung-Hwan Choi , Jin-Hyo Kim , Tae-Il Kim , Il-Hyun Cho , Sung-Joon Jang , Hye-Sun Kim , Jin-Kyoung Du
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval.
摘要翻译：多核系统中的中央处理单元（CPU）的功率控制方法。功率控制方法包括获取CPU的当前使用信息和系统信息，基于获取的当前使用信息估计下一时间间隔的CPU使用量，基于获取的系统信息校准下一时间间隔的估计CPU使用量，以及基于所获取的系统信息和下一时间间隔的校准CPU使用中的至少一个来确定功率控制模式。

4. 发明授权

US07131042B2 Semiconductor device and method for testing the same 有权
标题翻译：半导体装置及其测试方法
公开(公告)号：US07131042B2
公开(公告)日：2006-10-31
申请号：US10421533
申请日：2003-04-21
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G01R31/28
CPC分类号： G01R31/31926
摘要： Test board configurations and test method for semiconductor devices with simultaneous bi-directional (SBD) data ports are disclosed. The devices have two SBD data ports with a pass mode that relays data between the ports. Significantly, each device contains configurable switching elements that allow a test mode, wherein unidirectional input/output data on one SBD data port is mapped to bi-directional data on the other SBD data port. This allows device testing with automated test equipment that employs unidirectional data signaling, and yet allows such test equipment to test the SBD capability of such devices.
摘要翻译：公开了具有同时双向（SBD）数据端口的半导体器件的测试板配置和测试方法。这些设备具有两个SBD数据端口，通过模式在端口之间中继数据。重要的是，每个设备都包含允许测试模式的可配置开关元件，其中一个SBD数据端口上的单向输入/输出数据映射到另一个SBD数据端口上的双向数据。这允许使用采用单向数据信号的自动测试设备进行设备测试，并允许这种测试设备测试这些设备的SBD能力。

5. 发明授权

US07023742B2 Semiconductor device and method for inputting/outputting data simultaneously through single pad 有权
标题翻译：半导体装置和通过单个焊盘同时输入/输出数据的方法
公开(公告)号：US07023742B2
公开(公告)日：2006-04-04
申请号：US10819678
申请日：2004-04-06
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C11/4093 , G11C2207/005 , G11C2207/105
摘要： Provided are a semiconductor device and a method for inputting and outputting data simultaneously through a single bi-directional pad. The semiconductor device includes a bi-directional input/output pad including an output buffer and an input buffer, a data output line coupled to the output buffer, and a data input line coupled to the input buffer. A bit line sense amplifier is coupled to a plurality of bit lines. A first switching circuit is coupled to the data output line. And a second switching circuit is coupled to the data input line.
摘要翻译：提供了一种通过单个双向键盘同时输入和输出数据的半导体器件和方法。半导体器件包括双向输入/输出焊盘，其包括输出缓冲器和输入缓冲器，耦合到输出缓冲器的数据输出线以及耦合到输入缓冲器的数据输入线。位线读出放大器耦合到多个位线。第一开关电路耦合到数据输出线。并且第二开关电路耦合到数据输入线。

6. 发明授权

US06859078B2 Delay lock loop circuit 有权
标题翻译：延时锁回路电路
公开(公告)号：US06859078B2
公开(公告)日：2005-02-22
申请号：US10641313
申请日：2003-08-14
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： H03L7/22 , H03L7/07 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/07
摘要： A delay lock loop circuit includes a reference loop for receiving an external clock signal and for generating a second output signal and a first output signal which includes a plurality of signals having different respective phases. A fine loop receives the external clock signal and the first output signal of the reference loop and generates an internal clock signal. A transition detecting circuit receives the second output signal of the reference loop and generates a protection signal by detecting a transition of the logic state of the second output signal of the reference loop. In response to the protection signal, the delay lock loop circuit in accordance with the present invention protects itself from an external clock signal that has a frequency that is out of the range of operable frequencies of the delay lock loop circuit, for example by disabling the entire circuit, or a portion of the circuit.
摘要翻译：延迟锁定环电路包括用于接收外部时钟信号并用于产生第二输出信号的参考回路和包括具有不同相位相位的多个信号的第一输出信号。精细回路接收外部时钟信号和参考环路的第一个输出信号，并产生内部时钟信号。转移检测电路接收参考回路的第二输出信号，并通过检测参考回路的第二输出信号的逻辑状态的转变来产生保护信号。响应于保护信号，根据本发明的延迟锁定环路电路保护自身不具有超出延迟锁定环电路的可操作频率范围的频率的外部时钟信号，例如通过禁用整个电路或电路的一部分。

7. 发明授权

US06839786B2 Information processing system with memory modules of a serial bus architecture 有权
标题翻译：具有串行总线结构的存储器模块的信息处理系统
公开(公告)号：US06839786B2
公开(公告)日：2005-01-04
申请号：US10166258
申请日：2002-06-11
申请人： Kyung-Ho Kim , Jung-Hwan Choi , Nak-Won Heo
发明人： Kyung-Ho Kim , Jung-Hwan Choi , Nak-Won Heo
IPC分类号： G06F13/00 , G11C7/10 , G11C11/4076 , G11C11/409 , G06F1/04
CPC分类号： G11C11/409 , G11C7/1048 , G11C11/4076
摘要： An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

8. 发明授权

US06831478B2 Open drain type output buffer 有权
标题翻译：开漏型输出缓冲器
公开(公告)号：US06831478B2
公开(公告)日：2004-12-14
申请号：US10425824
申请日：2003-04-30
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： H03K19003
CPC分类号： H04L25/028 , H03K19/00323
摘要： The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.
摘要翻译：开漏型输出缓冲器包括第一驱动器，并且在（1）至少一个辅助驱动器的东侧和（2）至少一个第三驱动器的东一侧。第一个驱动器基于输入数据选择性地将输出节点拉向低电压。二级和三级驾驶员有第一和第二州。当处于第一状态时，每个次级和三级驱动器将输出节点拉向低电压，并且在第二状态下将输出节点拉向低电压。当包括次级驱动器时，控制电路控制次级驱动器，使得当已经确定已经生成了至少两个连续的低电压输出数据时，辅助驱动器处于第二状态。当包括三级驱动器时，控制电路控制第三驱动器，使得当确定从稳定的高电压输出数据到低电压输出数据的转变时，第三驱动器处于第一状态。

9. 发明授权

US08675428B2 Delay-locked-loop circuit 有权
标题翻译：延迟锁定环电路
公开(公告)号：US08675428B2
公开(公告)日：2014-03-18
申请号：US13729412
申请日：2012-12-28
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C8/00
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

10. 发明申请

US20120166896A1 METHOD AND APPARATUS FOR TRANSMITTING DATA BETWEEN TIMING CONTROLLER AND SOURCE DRIVER, HAVING BIT ERROR RATE TEST FUNCTION 有权
标题翻译：用于在时序控制器和源驱动器之间传输数据的方法和装置，具有位错误率测试功能
公开(公告)号：US20120166896A1
公开(公告)日：2012-06-28
申请号：US13333240
申请日：2011-12-21
申请人： Kwang-Il Oh , Yun-Tack Han , Soo-Woo Kim , Jung-Hwan Choi , Hyun-Kyu Jeon , Joon-Ho Na
发明人： Kwang-Il Oh , Yun-Tack Han , Soo-Woo Kim , Jung-Hwan Choi , Hyun-Kyu Jeon , Joon-Ho Na
IPC分类号： G06F11/00
CPC分类号： G09G5/18 , G09G5/006 , G09G5/008 , G09G2310/08 , G09G2330/12
摘要： Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.
摘要翻译：公开了一种用于在定时控制器和源驱动器之间传输数据的方法和装置，更具体地说，涉及一种定时控制器和源驱动器之间的数据传输方法和装置，它具有用于传感的误码率测试（BERT）功能在定时控制器和源驱动器之间发送和接收数据时，实时出现错误率。

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