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1. 发明授权

US08255622B2 Memory controller and data processing system 有权
标题翻译：内存控制器和数据处理系统
公开(公告)号：US08255622B2
公开(公告)日：2012-08-28
申请号：US13233308
申请日：2011-09-15
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0215 , G11C7/1018 , Y02D10/13 , Y02D10/14
摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
摘要翻译：存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问在高速和低功耗下。

2. 发明授权

US07613880B2 Memory module, memory system, and information device 有权
标题翻译：内存模块，内存系统和信息设备
公开(公告)号：US07613880B2
公开(公告)日：2009-11-03
申请号：US10536460
申请日：2003-11-27
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G11C11/005 , G06F12/0638 , G06F2212/2022 , G11C7/20 , G11C11/4072 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.
摘要翻译：提供了包括大容量ROM和RAM的存储器系统，其中启用了高速读写。配置包括非易失性存储器（CHIP1），DRAM（CHIP3），控制电路（CHIP2）和信息处理设备（CHIP4））的存储器系统。 FLASH中的数据提前传输到SRAM或DRAM，以加快速度。在非易失性存储器（FLASH）和DRAM（CHIP3）之间的数据传输可以在后台执行。包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 FLASH中的数据可以通过保护FLASH中的数据可以在DRAM中复制的区域以及在接通电源或通过加载指令之后将数据传送到DRAM中，以与DRAM类似的速度读取速度。

3. 发明授权

US07554872B2 Semiconductor device including multi-chip 有权
公开(公告)号：US07554872B2
公开(公告)日：2009-06-30
申请号：US11037088
申请日：2005-01-19
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

4. 发明授权

US07136978B2 System and method for using dynamic random access memory and flash memory 有权
标题翻译：使用动态随机存取存储器和闪存的系统和方法
公开(公告)号：US07136978B2
公开(公告)日：2006-11-14
申请号：US10445922
申请日：2003-05-28
申请人： Seiji Miura , Kazushige Ayukawa , Tetsuya Iwamura
发明人： Seiji Miura , Kazushige Ayukawa , Tetsuya Iwamura
IPC分类号： G06F12/00 , G06F12/02 , G06F12/16
CPC分类号： G06F11/1068 , G06F12/0638 , Y02D10/13
摘要： A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.
摘要翻译：提供了一种使用动态随机存取存储器和闪速存储器的系统和方法。在一个示例中，存储器系统包括非易失性存储器; 同步动态随机存取存储器; 包括与非易失性存储器和同步动态随机存取存储器耦合的控制电路的电路，并控制对非易失性存储器和同步动态随机存取存储器的访问; 以及与电路耦合的多个输入/输出端子，其中在从非易失性存储器到同步动态随机存取存储器的数据传输中，传送纠错数据。

5. 发明授权

US06574700B2 Semiconductor device with auto address allocation means for a cache memory 有权
标题翻译：具有用于高速缓冲存储器的自动地址分配装置
公开(公告)号：US06574700B2
公开(公告)日：2003-06-03
申请号：US09986347
申请日：2001-11-08
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F1200
CPC分类号： G06F13/161 , G06F12/0215 , G11C7/1018 , Y02D10/13 , Y02D10/14
摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
摘要翻译：存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问在高速和低功耗下。

6. 发明授权

US06392950B2 Semiconductor device including multi-chip 有权
标题翻译：半导体器件包括多芯片
公开(公告)号：US06392950B2
公开(公告)日：2002-05-21
申请号：US09803958
申请日：2001-06-29
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C800
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

7. 发明申请

US20110258373A1 Memory Module, Memory System,and Information Device 失效
标题翻译：内存模块，内存系统和信息设备
公开(公告)号：US20110258373A1
公开(公告)日：2011-10-20
申请号：US13169912
申请日：2011-06-27
申请人： Seiji MIURA , Kazushige Ayukawa
发明人： Seiji MIURA , Kazushige Ayukawa
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G11C11/005 , G06F12/0638 , G06F2212/2022 , G11C7/20 , G11C11/4072 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.
摘要翻译：包括ROM和RAM的存储器系统，其中启用读和写。存储器系统包括非易失性存储器（FLASH），DRAM，控制电路和信息处理设备。预先将FLASH中的数据传送到SRAM或DRAM。在非易失性存储器和DRAM之间的数据传输可以在后台执行。包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 FLASH中的数据可以通过保护FLASH中的数据可以在DRAM中复制的区域以及在接通电源或通过加载指令之后将数据传送到DRAM中，以与DRAM类似的速度读取速度。

8. 发明授权

US08024512B2 Memory controller and data processing system 有权
标题翻译：内存控制器和数据处理系统
公开(公告)号：US08024512B2
公开(公告)日：2011-09-20
申请号：US12620912
申请日：2009-11-18
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0215 , G11C7/1018 , Y02D10/13 , Y02D10/14
摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
摘要翻译：存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问在高速和低功耗下。

9. 发明申请

US20070101088A1 Semiconductor intergrated circuit and data processing system 有权
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US20070101088A1
公开(公告)日：2007-05-03
申请号：US11641808
申请日：2006-12-20
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F13/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译：为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。数据保存在每个存储体的读出放大器中。当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。即，使每个存储体用作读出放大器高速缓存。为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据地址由另一个存储体中的读出放大器预读。

10. 发明授权

US07165151B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US07165151B2
公开(公告)日：2007-01-16
申请号：US11010324
申请日：2004-12-14
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

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