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1. 发明申请

US20130026961A1 INJECTION MOLDING MACHINE 有权
标题翻译：注塑机
公开(公告)号：US20130026961A1
公开(公告)日：2013-01-31
申请号：US13556320
申请日：2012-07-24
申请人： Noritaka OKADA , Hiroshi MORITA , Hiroyuki MIZUNO , Atsushi KATO
发明人： Noritaka OKADA , Hiroshi MORITA , Hiroyuki MIZUNO , Atsushi KATO
IPC分类号： H02P6/00
CPC分类号： H02P6/00 , B29C45/7666 , B29C2045/1792 , B29C2045/7673 , Y02P70/26 , Y02P70/261
摘要： An injection molding machine includes a motor; a driver circuit; a rectifying part; a capacitor provided between the driver circuit and the rectifying part; a bridge circuit that converts direct electric power between the driver circuit and the rectifying part into alternating electric power; a harmonics component reducing part connected to an alternating side of the bridge circuit; and a regenerative line connected to the rectifying part in parallel, wherein the bridge circuit and the harmonics component reducing part are provided in the regenerative line, and plural switching elements of the bridge circuit are turned on or off such that electric power of the motor is regenerated when a voltage of the capacitor is greater than or equal to a predetermined value, and all the switching elements are turned off when the voltage of the capacitor is less than the predetermined value.
摘要翻译：注射成型机包括马达; 驱动电路; 整改部分设置在驱动电路和整流部之间的电容器; 将驱动电路和整流部之间的直接电力转换为交流电力的桥式电路; 连接到桥接电路的交替侧的谐波分量减少部分; 以及并联连接到整流部的再生线，其中，所述桥接电路和所述谐波成分减少部设置在所述再生线路中，所述桥接电路的多个开关元件导通或截止，使得所述电动机的电力为当电容器的电压大于或等于预定值时再生，并且当电容器的电压小于预定值时，所有开关元件都截止。

2. 发明申请

US20130026956A1 INJECTION MOLDING MACHINE 有权
标题翻译：注塑机
公开(公告)号：US20130026956A1
公开(公告)日：2013-01-31
申请号：US13556305
申请日：2012-07-24
申请人： Atsushi KATO , Hiroshi MORITA , Hiroyuki MIZUNO , Noritaka OKADA
发明人： Atsushi KATO , Hiroshi MORITA , Hiroyuki MIZUNO , Noritaka OKADA
IPC分类号： H02P3/14
CPC分类号： H02P6/00 , B29C45/7666 , B29C2045/1792 , B29C2045/7673 , Y02P70/26 , Y02P70/261
摘要： An injection molding machine according to the invention includes a motor, a driver circuit that drives the motor; and a rectifying part that supplies electric power to the driver circuit. A regenerative line for regenerative electric power of the motor is connected to the rectifying part in parallel. A converting part and a harmonics component reducing part are provided in the regenerative line. The converting part converts direct electric power between the driver circuit and the rectifying part into alternating electric power which is input to the harmonics component reducing part.
摘要翻译：根据本发明的注射成型机包括马达，驱动马达的驱动电路; 以及向驱动电路供给电力的整流部。马达的再生电力再生线并联连接到整流部。在再生线路中设置A转换部和谐波成分减少部。转换部分将驱动电路和整流部分之间的直接电力转换为输入到谐波分量减少部分的交流电力。

3. 发明授权

US08222945B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08222945B2
公开(公告)日：2012-07-17
申请号：US13253584
申请日：2011-10-05
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

4. 发明授权

US08199217B2 Device and method for image processing, program, and imaging apparatus 有权
标题翻译：用于图像处理，程序和成像装置的装置和方法
公开(公告)号：US08199217B2
公开(公告)日：2012-06-12
申请号：US12461406
申请日：2009-08-11
申请人： Hiroyuki Mizuno , Satoshi Terada
发明人： Hiroyuki Mizuno , Satoshi Terada
IPC分类号： H04N9/73 , H04N9/64 , H04N5/222 , G06K9/00
CPC分类号： H04N9/735 , H04N5/144
摘要： An image processing device includes a white balancing unit configured to perform white balancing on an image signal within a pull-in frame defined by the color temperature of a light source to output the resultant signal, and a control unit configured to, when the white balancing unit performs white balancing on an image signal obtained by capturing an image of a subject illuminated by light emitted from a light emitting device, adjust a region of the pull-in frame on the basis of color information of a light emission signal output from the light emitting device.
摘要翻译：一种图像处理装置，包括白平衡单元，被配置为对由光源的色温定义的拉入框内的图像信号执行白平衡，以输出结果信号;以及控制单元，被配置为当白平衡通过拍摄由从发光装置发出的光照射的被摄体的图像而获得的图像信号进行白平衡，基于从光输出的发光信号的颜色信息来调整拉入框的区域发光装置。

5. 发明申请

US20110199708A1 LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING THE LEVEL CONVERSION CIRCUIT 有权
标题翻译：使用电平转换电路的电平转换电路和半导体集成电路设备
公开(公告)号：US20110199708A1
公开(公告)日：2011-08-18
申请号：US13095480
申请日：2011-04-27
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H02H9/04 , H01L23/60
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

6. 发明授权

US07990208B2 Voltage supply with low power and leakage current 有权
标题翻译：电源电压低，漏电流小
公开(公告)号：US07990208B2
公开(公告)日：2011-08-02
申请号：US12591146
申请日：2009-11-10
申请人： Hiroyuki Mizuno , Kiyoo Itoh
发明人： Hiroyuki Mizuno , Kiyoo Itoh
IPC分类号： G05F1/575 , G11C11/4074
CPC分类号： G11C11/413 , G05F3/262 , G11C5/147
摘要： In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.
摘要翻译：在半导体集成电路器件中，电路块具有第一MOS晶体管，并且具有第二MOS晶体管和电流源的漏电流控制电路，第二MOS晶体管的源极和漏极电路形成在第二MOS晶体管的电源线之间电路块和提供工作电压的电压点。该电流源连接到电源线，并且在第一状态下，电源线被第二MOS晶体管驱动到第一电压。在第二状态下，通过电流源中的电流将电源线控制在第二电压，并且在第二状态下施加在第一MOS晶体管的源极和漏极两端的电压小于施加在源极上的电压和第一状态的第一MOS晶体管的漏极。

7. 发明申请

US20110017176A1 ABNORMALITY DIAGNOSING SYSTEM FOR INTERNAL COMBUSTION ENGINE 有权
标题翻译：内燃机异常诊断系统
公开(公告)号：US20110017176A1
公开(公告)日：2011-01-27
申请号：US12822637
申请日：2010-06-24
申请人： Hiroyuki Mizuno , Naoya Okubo
发明人： Hiroyuki Mizuno , Naoya Okubo
IPC分类号： F02M51/00 , G01M15/04
CPC分类号： F02M69/044 , F02D41/221 , F02D41/3094 , F02D41/40 , F02D2200/1015 , F02M69/046 , G01M15/11 , Y02T10/44
摘要： An abnormality diagnosing system for an internal combustion engine including a first fuel injection valve that injects fuel into a cylinder, and a second fuel injection valve that injects fuel into an intake passage is provided which has a control device controls an injection pattern of the first fuel injection valve and the second fuel injection valve. The control device stores engine operating conditions when an abnormality occurs in the engine, and make a return-to-normal determination as to whether the engine returns to a normal operating state when similar operation conditions that are the same as or within predetermined ranges of the stored operating conditions are established. The injection pattern is selected from patterns in which the fuel is injected solely from the first fuel injection valve, solely from the second fuel injection valve, and from both of the first and second fuel injection valves. The control device stores the injection pattern when the abnormality occurs, and makes a return-to-normal determination on condition that the engine is operating in an injection pattern that is the same as the stored injection pattern.
摘要翻译：一种用于内燃机的异常诊断系统，包括：将燃料喷射到气缸中的第一燃料喷射阀和将燃料喷射到进气通道中的第二燃料喷射阀，其具有控制装置，其控制第一燃料的喷射模式喷射阀和第二燃料喷射阀。控制装置在发动机发生异常的情况下存储发动机工作状态，并且在与所述发动机的预定范围相同或者在规定范围内的相似的运转条件下进行关于发动机是否恢复正常运转状态的返回正常判定存储操作条件建立。从仅从第一燃料喷射阀仅从第一燃料喷射阀喷射燃料的模式，仅从第二燃料喷射阀以及从第一和第二燃料喷射阀两者中选择喷射模式。当异常发生时，控制装置存储喷射模式，并且在发动机以与所存储的喷射模式相同的喷射模式操作的条件下进行归一正常确定。

8. 发明申请

US20100309741A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100309741A1
公开(公告)日：2010-12-09
申请号：US12859445
申请日：2010-08-19
申请人： HIROYUKI MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： HIROYUKI MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

9. 发明授权

US07814343B2 Semiconductor integrated circuit for reducing power consumption and enhancing processing speed 失效
标题翻译：半导体集成电路，用于降低功耗并提高处理速度
公开(公告)号：US07814343B2
公开(公告)日：2010-10-12
申请号：US11605362
申请日：2006-11-29
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3293 , G06F1/3203 , H01L21/823462 , Y02D10/122 , Y02D10/126
摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

10. 发明申请

US20100005324A1 SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 失效
标题翻译：用于低功率处理器的基板偏置开关单元
公开(公告)号：US20100005324A1
公开(公告)日：2010-01-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

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