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1. 发明授权

US08217463B2 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
标题翻译：用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法
公开(公告)号：US08217463B2
公开(公告)日：2012-07-10
申请号：US13021403
申请日：2011-02-04
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L29/66
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
摘要翻译：提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

2. 发明授权

US08193592B2 MOSFET with asymmetrical extension implant 有权
标题翻译：具有不对称延伸植入物的MOSFET
公开(公告)号：US08193592B2
公开(公告)日：2012-06-05
申请号：US12904662
申请日：2010-10-14
申请人： Frank Bin Yang , Andrew M. Waite , Scott Luning
发明人： Frank Bin Yang , Andrew M. Waite , Scott Luning
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/26586 , H01L29/66659 , H01L29/7834 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
摘要翻译：一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。以非零倾角进行离子注入工艺。在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

3. 发明申请

US20110169073A1 TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD 有权
标题翻译：具有非对称嵌入式应变元件的晶体管器件及相关制造方法
公开(公告)号：US20110169073A1
公开(公告)日：2011-07-14
申请号：US13052969
申请日：2011-03-21
申请人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
发明人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/665 , H01L29/66659 , H01L29/7848
摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
摘要翻译：提供半导体晶体管器件及相关制造方法。示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。晶体管器件还包括形成在凹槽中的应力诱导半导体材料。应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

4. 发明申请

US20110062498A1 EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY 有权
标题翻译：嵌入式硅锗锗排水结构，具有降低的硅胶密封性和接触电阻和增强的通道移动性
公开(公告)号：US20110062498A1
公开(公告)日：2011-03-17
申请号：US12561685
申请日：2009-09-17
申请人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
发明人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.
摘要翻译：具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。％，第二层的锗浓度大于第一层的浓度。实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。％锗，并且每个偶数层具有较高的锗浓度。实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

5. 发明授权

US07670934B1 Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions 有权
标题翻译：制造具有外延生长的应力诱导源极和漏极区域的MOS器件的方法
公开(公告)号：US07670934B1
公开(公告)日：2010-03-02
申请号：US12359764
申请日：2009-01-26
申请人： Rohit Pal , Frank Bin Yang
发明人： Rohit Pal , Frank Bin Yang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84
摘要： Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.
摘要翻译：提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

6. 发明申请

US20100012988A1 METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：带有碳化硅扩散层的金属氧化物半导体器件及其制造方法
公开(公告)号：US20100012988A1
公开(公告)日：2010-01-21
申请号：US12176916
申请日：2008-07-21
申请人： Frank Bin YANG , Michael J. HARGROVE , Rohit PAL
发明人： Frank Bin YANG , Michael J. HARGROVE , Rohit PAL
IPC分类号： H01L29/00 , H01L21/8236
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.
摘要翻译：提供了用于制造半导体器件的半导体器件和方法。一种示例性方法包括提供具有第一表面的含硅衬底，将凹陷蚀刻到第一表面中，凹部具有侧表面和底表面，将碳离子注入侧表面和底表面，以及形成杂质掺杂的，覆盖侧表面和底表面的含硅区域。

7. 发明申请

US20100012975A1 TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD 有权
标题翻译：具有非对称嵌入式应变元件的晶体管器件及相关制造方法
公开(公告)号：US20100012975A1
公开(公告)日：2010-01-21
申请号：US12176835
申请日：2008-07-21
申请人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
发明人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/665 , H01L29/66659 , H01L29/7848
摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
摘要翻译：提供半导体晶体管器件及相关制造方法。示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。晶体管器件还包括形成在凹槽中的应力诱导半导体材料。应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

8. 发明申请

US20120129311A1 METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS 有权
标题翻译：制造具有非对称嵌入式应变元件的晶体管器件的方法
公开(公告)号：US20120129311A1
公开(公告)日：2012-05-24
申请号：US13355221
申请日：2012-01-20
申请人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
发明人： Rohit PAL , Frank Bin YANG , Michael J. HARGROVE
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/665 , H01L29/66659 , H01L29/7848
摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
摘要翻译：提供半导体晶体管器件及相关制造方法。示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。晶体管器件还包括形成在凹槽中的应力诱导半导体材料。应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

9. 发明授权

US07994014B2 Semiconductor devices having faceted silicide contacts, and related fabrication methods 有权
标题翻译：具有多面体硅化物接触的半导体器件及相关制造方法
公开(公告)号：US07994014B2
公开(公告)日：2011-08-09
申请号：US12249570
申请日：2008-10-10
申请人： Frank Bin Yang , Rohit Pal , Michael J. Hargrove
发明人： Frank Bin Yang , Rohit Pal , Michael J. Hargrove
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/02381 , H01L21/02433 , H01L21/02529 , H01L21/02532 , H01L21/02609 , H01L21/02636 , H01L29/045 , H01L29/41766 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.
摘要翻译：所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。沟道区形成在半导体材料层中，栅极结构下方的沟道区。半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

10. 发明授权

US07939852B2 Transistor device having asymmetric embedded strain elements and related manufacturing method 有权
标题翻译：具有不对称嵌入式应变元件的晶体管器件及相关制造方法
公开(公告)号：US07939852B2
公开(公告)日：2011-05-10
申请号：US12176835
申请日：2008-07-21
申请人： Rohit Pal , Frank Bin Yang , Michael J. Hargrove
发明人： Rohit Pal , Frank Bin Yang , Michael J. Hargrove
IPC分类号： H01L31/0328
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/665 , H01L29/66659 , H01L29/7848
摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
摘要翻译：提供半导体晶体管器件及相关制造方法。示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。晶体管器件还包括形成在凹槽中的应力诱导半导体材料。应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

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