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1. 发明授权

US07521380B2 Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors 有权
标题翻译：制造具有窄间距和宽间距晶体管的应力增强型半导体器件的方法
公开(公告)号：US07521380B2
公开(公告)日：2009-04-21
申请号：US11738828
申请日：2007-04-23
申请人： Andrew M. Waite , Scott Luning , Frank (Bin) Yang
发明人： Andrew M. Waite , Scott Luning , Frank (Bin) Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.
摘要翻译：提供了一种在半导体衬底上制造半导体器件的方法。在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。去除覆盖在NPT上的蚀刻停止层的暴露部分。

2. 发明授权

US08193592B2 MOSFET with asymmetrical extension implant 有权
标题翻译：具有不对称延伸植入物的MOSFET
公开(公告)号：US08193592B2
公开(公告)日：2012-06-05
申请号：US12904662
申请日：2010-10-14
申请人： Frank Bin Yang , Andrew M. Waite , Scott Luning
发明人： Frank Bin Yang , Andrew M. Waite , Scott Luning
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/26586 , H01L29/66659 , H01L29/7834 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
摘要翻译：一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。以非零倾角进行离子注入工艺。在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

3. 发明授权

US07829401B2 MOSFET with asymmetrical extension implant 有权
标题翻译：具有不对称延伸植入物的MOSFET
公开(公告)号：US07829401B2
公开(公告)日：2010-11-09
申请号：US12121387
申请日：2008-05-15
申请人： Frank Bin Yang , Andrew M. Waite , Scott Luning
发明人： Frank Bin Yang , Andrew M. Waite , Scott Luning
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/26586 , H01L29/66659 , H01L29/7834 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
摘要翻译：一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。以非零倾角进行离子注入工艺。在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

4. 发明授权

US06972478B1 Integrated circuit and method for its manufacture 失效
标题翻译：集成电路及其制造方法
公开(公告)号：US06972478B1
公开(公告)日：2005-12-06
申请号：US11075774
申请日：2005-03-07
申请人： Andrew M. Waite , Scott Luning
发明人： Andrew M. Waite , Scott Luning
IPC分类号： H01L21/20 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/78
CPC分类号： H01L29/045 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/7833
摘要： An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of crystalline orientation and a second region of crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of crystalline orientation.
摘要翻译：提供集成电路及其制造方法。集成电路包括具有<100>晶体取向的第一区域和<110>晶体取向的第二区域的体硅衬底。绝缘体上的一层覆盖在体硅衬底的一部分上。在绝缘体上的硅层中形成至少一个场效应晶体管，在<110>晶取向的第二区域中形成至少一个P沟道场效应晶体管，并形成至少一个N沟道场效应晶体管在<100>晶体取向的第一区域。

5. 发明授权

US08148214B2 Stressed field effect transistor and methods for its fabrication 有权
标题翻译：强调场效应晶体管及其制造方法
公开(公告)号：US08148214B2
公开(公告)日：2012-04-03
申请号：US12360961
申请日：2009-01-28
申请人： Andrew M. Waite , Scott Luning
发明人： Andrew M. Waite , Scott Luning
IPC分类号： H01L21/00
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.
摘要翻译：提供了一种应力场效应晶体管及其制造方法。场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

6. 发明授权

US07504301B2 Stressed field effect transistor and methods for its fabrication 有权
标题翻译：强调场效应晶体管及其制造方法
公开(公告)号：US07504301B2
公开(公告)日：2009-03-17
申请号：US11536126
申请日：2006-09-28
申请人： Andrew M. Waite , Scott Luning
发明人： Andrew M. Waite , Scott Luning
IPC分类号： H01L21/00
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.
摘要翻译：提供了一种应力场效应晶体管及其制造方法。场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

7. 发明授权

US07183169B1 Method and arrangement for reducing source/drain resistance with epitaxial growth 有权
标题翻译：用外延生长降低源/漏电阻的方法和装置
公开(公告)号：US07183169B1
公开(公告)日：2007-02-27
申请号：US11072312
申请日：2005-03-07
申请人： Andrew M. Waite , Scott Luning , Philip A. Fisher
发明人： Andrew M. Waite , Scott Luning , Philip A. Fisher
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L29/665 , H01L29/66628
摘要： A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.
摘要翻译：用于降低MOSFET器件中的源极和漏极的串联电阻的方法和装置提供了在源极和漏极延伸部的顶部上的外延生长区域，以覆盖形成在衬底上的硅化物区域的顶表面的部分。外延材料提供了一个额外的流动路径，用于电流从延伸部分流到硅化物，以及增加源极/漏极和硅化物之间的表面积，以减少源极/漏极和硅化物之间的接触电阻。

8. 发明申请

US20080079033A1 STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
标题翻译：应力场效应晶体管及其制造方法
公开(公告)号：US20080079033A1
公开(公告)日：2008-04-03
申请号：US11536126
申请日：2006-09-28
申请人： Andrew M. Waite , Scott Luning
发明人： Andrew M. Waite , Scott Luning
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.
摘要翻译：提供了一种应力场效应晶体管及其制造方法。场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

9. 发明授权

US07977180B2 Methods for fabricating stressed MOS devices 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US07977180B2
公开(公告)日：2011-07-12
申请号：US12330296
申请日：2008-12-08
申请人： Andrew M. Waite , Andy C. Wei
发明人： Andrew M. Waite , Andy C. Wei
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.
摘要翻译：提供制造应力MOS器件的方法。在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。在凹部内形成拉伸应力诱发材料。

10. 发明申请

US20100144105A1 METHODS FOR FABRICATING STRESSED MOS DEVICES 有权
标题翻译：用于制作受压MOS器件的方法
公开(公告)号：US20100144105A1
公开(公告)日：2010-06-10
申请号：US12330296
申请日：2008-12-08
申请人： Andrew M. Waite , Andy C. Wei
发明人： Andrew M. Waite , Andy C. Wei
IPC分类号： H01L21/8238 , H01L21/8232
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.
摘要翻译：提供制造应力MOS器件的方法。在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。在凹部内形成拉伸应力诱发材料。

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