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1. 发明申请

US20120228716A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 审中-公开
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20120228716A1
公开(公告)日：2012-09-13
申请号：US13478400
申请日：2012-05-23
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.
摘要翻译：包括在NFET的沟道中具有嵌入硅锗（SiGe）插头的NFET的结构; 具有SiGe沟道的PFET; 以及在NFET和PFET之间的沟槽隔离，其中NFET和PFET没有SiGe外延生长边缘效应。

2. 发明申请

US20120104507A1 METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
标题翻译：在门电路第一流程中生长应变诱导材料的方法
公开(公告)号：US20120104507A1
公开(公告)日：2012-05-03
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

3. 发明申请

US20080268609A1 STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON 失效
标题翻译：封装在外延硅中的故障减少
公开(公告)号：US20080268609A1
公开(公告)日：2008-10-30
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/76
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

4. 发明申请

US20070072380A1 Methods for fabrication of a stressed MOS device 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US20070072380A1
公开(公告)日：2007-03-29
申请号：US11235791
申请日：2005-09-26
申请人： Frank Wirbeleit , Linda Black , Igor Peidous
发明人： Frank Wirbeleit , Linda Black , Igor Peidous
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/1037 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.
摘要翻译：提供制造应力MOS器件的方法。一种方法包括提供具有表面和邻接表面的通道的单晶半导体衬底的步骤。具有第一边缘和第二边缘的栅电极形成在单晶半导体衬底上。基板被各向异性蚀刻以形成与第一边缘对准的第一凹部和与第二边缘对准的第二凹部。衬底被进一步各向同性蚀刻以在通道下延伸的衬底中形成第三凹槽。第三凹部填充有膨胀材料以在通道上施加向上的力，并且第一和第二凹部填充有接触材料。电导率确定离子被注入到接触材料中以分别形成与第一和第二边缘对准的源极区域和漏极区域。

5. 发明申请

US20090181507A1 SIGE CHANNEL EPITAXIAL DEVELOPMENT FOR HIGH-K PFET MANUFACTURABILITY 失效
标题翻译：用于高K PFET制造商的信号通道外延开发
公开(公告)号：US20090181507A1
公开(公告)日：2009-07-16
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属栅极不同的功函数。

6. 发明申请

US20080083952A1 SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：包括多个晶体学方位的半导体结构及其制造方法
公开(公告)号：US20080083952A1
公开(公告)日：2008-04-10
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

7. 发明申请

US20080006876A1 STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON 有权
标题翻译：封装在外延硅中的故障减少
公开(公告)号：US20080006876A1
公开(公告)日：2008-01-10
申请号：US11456326
申请日：2006-07-10
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods and a structure are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法和结构。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

8. 发明申请

US20100283089A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 失效
标题翻译：通过退火减少堆叠不良的方法
公开(公告)号：US20100283089A1
公开(公告)日：2010-11-11
申请号：US12839588
申请日：2010-07-20
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

9. 发明申请

US20090294801A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 失效
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20090294801A1
公开(公告)日：2009-12-03
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092 , H01L21/205 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

10. 发明授权

US07494918B2 Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof 失效
标题翻译：包括多个晶体取向的半导体结构及其制造方法
公开(公告)号：US07494918B2
公开(公告)日：2009-02-24
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L21/4763 , H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

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