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1. 发明授权

US08503234B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08503234B2
公开(公告)日：2013-08-06
申请号：US13188869
申请日：2011-07-22
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , G11C16/06 , H01L29/792
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

2. 发明申请

US20110280072A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110280072A1
公开(公告)日：2011-11-17
申请号：US13188869
申请日：2011-07-22
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/08 , H01L29/788
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列译码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

3. 发明授权

US08400828B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08400828B2
公开(公告)日：2013-03-19
申请号：US13435901
申请日：2012-03-30
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

4. 发明申请

US20120195121A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120195121A1
公开(公告)日：2012-08-02
申请号：US13435901
申请日：2012-03-30
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

5. 发明授权

US08014198B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08014198B2
公开(公告)日：2011-09-06
申请号：US12411938
申请日：2009-03-26
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , G11C29/792 , G11C16/06
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

6. 发明申请

US20090180320A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090180320A1
公开(公告)日：2009-07-16
申请号：US12411938
申请日：2009-03-26
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

7. 发明授权

US06567312B1 Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor 失效
标题翻译：具有电荷存储绝缘膜的非易失性半导体存储器件及其数据保持方法
公开(公告)号：US06567312B1
公开(公告)日：2003-05-20
申请号：US09689714
申请日：2000-10-13
申请人： Satoshi Torii , Hideyuki Kojima , Hiroshi Mawatari
发明人： Satoshi Torii , Hideyuki Kojima , Hiroshi Mawatari
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/3454
摘要： In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.
摘要翻译：在具有例如由通过半导体衬底上的薄电荷陷阱层提供的栅极组成的单栅极型存储单元的闪存中，提供了一种非易失性半导体存储器，其特征在于施加短脉冲在将数据写入到存储单元之后，将其从电荷陷阱层部分去除。这确保了不改变存储单元阵列的基本结构的非易失性半导体存储器诸如单栅极型闪存等的写操作可靠性。

8. 发明授权

US07505328B1 Method and architecture for fast flash memory programming 有权
标题翻译：快速闪存编程的方法和架构
公开(公告)号：US07505328B1
公开(公告)日：2009-03-17
申请号：US11504254
申请日：2006-08-14
申请人： Satoshi Torii
发明人： Satoshi Torii
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.
摘要翻译：本发明的实施例公开了一种利用闪存阵列来减少编程时间同时保持足够的读取速度的方法。单元格阵列被编程和读取在与列方向相对齐的页面上，与阵列中的位线平行。本发明中的擦除单元是处于“关闭”状态的单元。根据本发明，通过降低电池的阈值电压来编程电池，从而使电池“接通”。单元阵列以逐扇区方式被读取，其中扇区由彼此对角地相邻的单元组成，并且单元由多个平行的列为列的页组成。

9. 发明授权

US07416940B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07416940B1
公开(公告)日：2008-08-26
申请号：US11418352
申请日：2006-05-03
申请人： Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
发明人： Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.
摘要翻译：提供了制造闪速存储器件的方法。一种方法包括形成覆盖衬底的多个栅叠层。每个栅极堆叠包括电荷捕获层和控制栅极。控制栅极是离基板的第一距离。相邻的门堆叠是第二个距离。沉积电池间隔物材料层并被蚀刻以形成围绕每个栅极叠层的侧壁的间隔物。在第一栅极堆叠和最后一个栅极堆叠附近形成源极/漏极杂质掺杂区域。第一距离和第二距离使得当在读取操作期间将电压施加到栅极堆叠时，在栅极堆叠的控制栅极和衬底之间产生边缘场，并且足以将一部分栅极堆叠和相邻栅极堆叠之间的衬底。

10. 发明申请

US20070175659A1 Printed circuit board 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20070175659A1
公开(公告)日：2007-08-02
申请号：US11655877
申请日：2007-01-22
申请人： Satoshi Torii
发明人： Satoshi Torii
IPC分类号： H05K1/16
CPC分类号： H05K1/111 , H05K3/3468 , H05K2201/09781 , H05K2201/10689 , H05K2203/046 , Y02P70/611
摘要： Disclosed herein is a printed circuit board that allows a wiring pattern to be resistant to noise while maintaining solderability even in the case where a wiring pattern is drawn out from the lower part of a QFP. A printed circuit board on which a QFP is mounted by dip soldering is provided with two separate solder flow lands formed between a front soldering land group and a rear soldering land group and a wiring pattern formed between the two separate solder flow lands, wherein the wiring pattern is a land having a width of not less than 0.3 mm, and a space between the wiring pattern and the solder flow lands is not less than 0.4 mm nor more than 0.8 mm.
摘要翻译：这里公开了一种印刷电路板，即使在从QFP的下部引出布线图案的情况下，也能够在保持可焊性的同时，使布线图案耐噪声化。通过浸焊在其上安装有QFP的印刷电路板设置有形成在前焊接组和后焊盘组之间的两个单独的焊料流动台面和形成在两个分离的焊料焊盘之间的布线图案，其中布线图案是具有不小于0.3mm的宽度的焊盘，并且布线图案和焊料流焊台之间的间隔不小于0.4mm，也不大于0.8mm。

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