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1. 发明授权

US08503234B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08503234B2
公开(公告)日：2013-08-06
申请号：US13188869
申请日：2011-07-22
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , G11C16/06 , H01L29/792
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

2. 发明申请

US20110280072A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110280072A1
公开(公告)日：2011-11-17
申请号：US13188869
申请日：2011-07-22
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/08 , H01L29/788
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列译码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

3. 发明授权

US08400828B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08400828B2
公开(公告)日：2013-03-19
申请号：US13435901
申请日：2012-03-30
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

4. 发明申请

US20120195121A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120195121A1
公开(公告)日：2012-08-02
申请号：US13435901
申请日：2012-03-30
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

5. 发明授权

US08014198B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08014198B2
公开(公告)日：2011-09-06
申请号：US12411938
申请日：2009-03-26
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , G11C29/792 , G11C16/06
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

6. 发明申请

US20090180320A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090180320A1
公开(公告)日：2009-07-16
申请号：US12411938
申请日：2009-03-26
申请人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
发明人： Satoshi Torii , Kazuhiro Mizutani , Toshio Nomura , Masayoshi Asano , Ikuto Fukuoka , Hiroshi Mawatari , Motoi Takahashi
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
摘要翻译：一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

7. 发明授权

US06567312B1 Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor 失效
标题翻译：具有电荷存储绝缘膜的非易失性半导体存储器件及其数据保持方法
公开(公告)号：US06567312B1
公开(公告)日：2003-05-20
申请号：US09689714
申请日：2000-10-13
申请人： Satoshi Torii , Hideyuki Kojima , Hiroshi Mawatari
发明人： Satoshi Torii , Hideyuki Kojima , Hiroshi Mawatari
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/3454
摘要： In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.
摘要翻译：在具有例如由通过半导体衬底上的薄电荷陷阱层提供的栅极组成的单栅极型存储单元的闪存中，提供了一种非易失性半导体存储器，其特征在于施加短脉冲在将数据写入到存储单元之后，将其从电荷陷阱层部分去除。这确保了不改变存储单元阵列的基本结构的非易失性半导体存储器诸如单栅极型闪存等的写操作可靠性。

8. 发明申请

US20070133303A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20070133303A1
公开(公告)日：2007-06-14
申请号：US11607090
申请日：2006-12-01
申请人： Hiroshi Mawatari , Norito Hibino , Naoto Emi
发明人： Hiroshi Mawatari , Norito Hibino , Naoto Emi
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value,- a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.
摘要翻译：非易失性评估存储单元分别被预先编程为多个不同的值。内部电压产生电路可以根据调整信号改变内部电压的值。为了使内部电压接近其预期值， - 电压调整电路根据在评估存储器单元上的读取操作中分别流过评估存储器单元的单元电流输出调整信号。结果，由于制造条件的变化而从其期望值偏移的间隔电压可以通过使用调整信号而被自动设定为期望值。由于内部电路工作在正确的内部电压，因此可以增加操作余量。因此可以提高非易失性半导体存储器的产量。

9. 发明申请

US20060053399A1 Semiconductor device, designing device, layout designing method, program and storage medium 审中-公开
标题翻译：半导体器件，设计器件，布局设计方法，程序和存储介质
公开(公告)号：US20060053399A1
公开(公告)日：2006-03-09
申请号：US11014843
申请日：2004-12-20
申请人： Hiroyuki Honda , Toshio Arakawa , Hiroshi Mawatari , Norito Hibino , Kouji Arai , Keigo Tada , Fukuji Kihara
发明人： Hiroyuki Honda , Toshio Arakawa , Hiroshi Mawatari , Norito Hibino , Kouji Arai , Keigo Tada , Fukuji Kihara
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068
摘要： A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.
摘要翻译：用于设计半导体器件的布局的设计装置包括：布局位置候选提取单元，用于获得调节器的布局位置候选;暂时布线单元，用于暂时地将调节器布置在布局位置候选位置并暂时布置电力线;以及调节器布置位置决定单元，用于决定暂时布置的电力线的区域最小的暂定布局的位置作为调节器的布局位置。

10. 发明授权

US07986561B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07986561B2
公开(公告)日：2011-07-26
申请号：US12388873
申请日：2009-02-19
申请人： Hiroshi Mawatari
发明人： Hiroshi Mawatari
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3454 , G11C16/0433
摘要： A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including second gate insulation films and drive the control gate line and the source line with a boost voltage higher than the first driving voltage.
摘要翻译：半导体存储器件包括包括选择晶体管和存储晶体管的存储单元; 选择栅极线耦合到选择晶体管的栅极; 耦合到存储晶体管的控制栅极的控制栅极线; 源极线耦合到存储晶体管的源极; 耦合到选择晶体管的位线; 选择栅极线驱动电路; 控制栅线驱动电路; 以及源极线驱动电路，其中所述选择栅线驱动电路包括第一晶体管，所述第一晶体管包括第一栅极绝缘膜，并以第一驱动电压驱动所述选择栅极线，并且所述控制栅线驱动电路和所述源极线驱动电路包括第二晶体管，包括第二栅极绝缘膜，并以比第一驱动电压高的升压电压驱动控制栅线和源极线。

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