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1. 发明授权

US08868833B1 Processor and cache arrangement with selective caching between first-level and second-level caches 有权
标题翻译：处理器和高速缓存配置，在一级和二级缓存之间进行选择性缓存
公开(公告)号：US08868833B1
公开(公告)日：2014-10-21
申请号：US13196398
申请日：2011-08-02
申请人： David W. Bennett , Jeffrey M. Mason
发明人： David W. Bennett , Jeffrey M. Mason
IPC分类号： G06F12/02
CPC分类号： G06F12/0811 , G06F12/084
摘要： Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.
摘要翻译：在多处理器系统中缓存可寻址项目的方法。指令被缓存在分别耦合到多处理器系统的多个处理器的多个第一级指令高速缓存中。第一类型数据项被缓存在分别耦合到多个处理器的多个第一级数据高速缓存中。第二类型数据项被缓存在二级缓存中，并且不被高速缓存在多个第一级数据高速缓存中的任何一个中。

2. 发明授权

US08839004B1 Secure cloud computing infrastructure 有权
标题翻译：安全的云计算基础设施
公开(公告)号：US08839004B1
公开(公告)日：2014-09-16
申请号：US13447766
申请日：2012-04-16
申请人： David W. Bennett , Jeffrey M. Mason
发明人： David W. Bennett , Jeffrey M. Mason
IPC分类号： G06F12/14
CPC分类号： G06F21/575
摘要： In one embodiment, a system for secure application hosting is provided. The system includes a memory, a first processor coupled to the memory, a second processor coupled to the first processor via a bus, and a data storage device and a network interface coupled to the second processor. The second processor is configured to perform cryptographic processing to provide an encrypted domain, in which the network interface and data storage device operate, and an unencrypted domain, in which the processor and memory operate.
摘要翻译：在一个实施例中，提供了一种用于安全应用托管的系统。该系统包括存储器，耦合到存储器的第一处理器，经由总线耦合到第一处理器的第二处理器，以及耦合到第二处理器的数据存储设备和网络接口。第二处理器被配置为执行加密处理以提供其中网络接口和数据存储设备操作的加密域以及处理器和存储器在其中操作的未加密域。

3. 发明授权

US08473904B1 Generation of cache architecture from a high-level language description 有权
标题翻译：从高级语言描述生成缓存架构
公开(公告)号：US08473904B1
公开(公告)日：2013-06-25
申请号：US12009272
申请日：2008-01-16
申请人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
发明人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
IPC分类号： G06F9/44 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/44 , G06F8/433 , G06F12/00 , G06F13/00 , G06F13/28 , G06F17/5054
摘要： Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.
摘要翻译：描述从高级语言描述生成缓存体系结构。获得了以高级编程语言的应用程序的描述。从适于在硬件中提供实现的描述生成数据流表示。生成包括：识别与描述相关联的存储器的访问; 确定对存储器的至少一部分访问不具有用于本地可缓存数据的一个或多个数据依赖性; 并将该部分分配给分布式高速缓存。

4. 发明授权

US06817005B2 Modular design method and system for programmable logic devices 有权
标题翻译：可编程逻辑器件的模块化设计方法和系统
公开(公告)号：US06817005B2
公开(公告)日：2004-11-09
申请号：US09839464
申请日：2001-04-20
申请人： Jeffrey M. Mason , Steve E. Lass , Bruce E. Talley , David W. Bennett
发明人： Jeffrey M. Mason , Steve E. Lass , Bruce E. Talley , David W. Bennett
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , G06F17/5072
摘要： In modular design flow, logic designers are able to partition a top-level logic design for a PLD into modules and implement any module independently from other modules. Modules are mapped, placed, and routed using selected information derived at the time the top-level logic design is partitioned. Finally, the modules are integrated into the top-level logic design using a guided process. Specifically, the information generated during the partitioning of the top-level design and the implementation of each module is used to guide the implementation of the associated logic in the top-level design. In this manner, the implementation of all modules can proceed in any order or in parallel and the integration of the modules into the top-level design can be done quickly and in any order.
摘要翻译：在模块化设计流程中，逻辑设计人员可以将PLD的顶级逻辑设计分为模块，并独立于其他模块实现任何模块。使用在顶层逻辑设计分区时导出的所选信息对模块进行映射，放置和布线。最后，使用引导过程将模块集成到顶级逻辑设计中。具体来说，在顶层设计分区和每个模块的实现过程中生成的信息用于指导顶层设计中相关逻辑的实现。以这种方式，所有模块的实现可以以任何顺序或并行进行，并且将模块集成到顶层设计中可以以任何顺序快速完成。

5. 发明授权

US07917567B1 Floating-point processing unit for successive floating-point operations 有权
标题翻译：用于连续浮点运算的浮点处理单元
公开(公告)号：US07917567B1
公开(公告)日：2011-03-29
申请号：US11810719
申请日：2007-06-07
申请人： Jeffrey M. Mason , David W. Bennett
发明人： Jeffrey M. Mason , David W. Bennett
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/485 , G06F7/487
摘要： A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.
摘要翻译：用于一系列浮点运算的浮点处理单元。耦合指数调节器以接收数字输入并且被配置为从数字输入产生第一调整值。第一个调整值具有相应的第一个调整值之间的等效指数。第一操作特定浮点处理单元（OFPU）被耦合以接收第一调整值并且包括被配置用于对第一调整值进行第一浮点运算以提供第一数值结果的第一运算电路。第一个数值结果在第二个浮点运算之前没有被归一化。

6. 发明授权

US07817655B1 Determining sizes of FIFO buffers between functional blocks in an electronic circuit 有权
标题翻译：确定电子电路中功能块之间的FIFO缓冲区的大小
公开(公告)号：US07817655B1
公开(公告)日：2010-10-19
申请号：US12261191
申请日：2008-10-30
申请人： David W. Bennett , Jeffrey M. Mason
发明人： David W. Bennett , Jeffrey M. Mason
IPC分类号： H04L12/28
CPC分类号： G06F17/505
摘要： Approaches for sizing first-in-first-out (FIFO) buffers for pipelining functions of a circuit. Functions of the circuit are performed on an input data set, with respective FIFO buffers for buffering data elements between coupled pairs of the functional blocks. While performing the functions of the circuit, a respective current number of elements added to a FIFO buffer since a previous element was removed from the FIFO buffer is counted for each FIFO buffer, and then compared to a respective saved number. The respective current number is saved as a new respective saved number in response to the respective current number being greater than the respective saved number, and the respective current number is reset after the comparing of the respective current number to the respective saved number. Respective sizes for the FIFO buffers are determined as a function of the respective saved numbers and then the sizes are stored.
摘要翻译：用于调整电路功能的先进先出（FIFO）缓冲器的大小的方法。电路的功能在输入数据集上执行，各个FIFO缓冲器用于在功能块的耦合对之间缓冲数据元素。在执行电路的功能的同时，对于每个FIFO缓冲器，对从FIFO缓冲器中删除先前元素之后添加到FIFO缓冲器中的相应当前数量的元素进行计数，然后与相应保存的数量进行比较。响应于相应的当前号码大于相应保存的号码，相应的当前号码被保存为新的相应保存的号码，并且在相应的当前号码与相应保存的号码进行比较之后，各个当前号码被重置。根据相应保存的数字确定FIFO缓冲区的大小，然后存储大小。

7. 发明授权

US07930662B1 Methods for automatically generating fault mitigation strategies for electronic system designs 有权
标题翻译：自动生成电子系统设计故障缓解策略的方法
公开(公告)号：US07930662B1
公开(公告)日：2011-04-19
申请号：US12264283
申请日：2008-11-04
申请人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
发明人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.
摘要翻译：公开了用于产生电子系统设计的方法。在一种方法中，对于设计的第一规范的一个或多个组件中的每一个，响应于与设计的第一规范相关联的用户指定的数据，从多个不同的误差减轻技术中选择错误减轻技术。从第一规格自动生成设计的第二个规范。第二规范包括与针对所述一个或多个组件中的每个组件的每个所选择的误差减轻技术相对应的误差减轻逻辑设计的第二个规格被存储用于后续处理。

8. 发明授权

US08473880B1 Synchronization of parallel memory accesses in a dataflow circuit 有权
标题翻译：数据流电路中并行存储器访问的同步
公开(公告)号：US08473880B1
公开(公告)日：2013-06-25
申请号：US12791256
申请日：2010-06-01
申请人： David W. Bennett , Prasanna Sundararajan
发明人： David W. Bennett , Prasanna Sundararajan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/74
摘要： Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.
摘要翻译：从高级语言（HLL）规范创建流水线电路设计的方法。在一个实施例中，HLL规范被转换成流水线电路设计的操作的中间级语言规范，并且创建操作的数据依赖图。识别由两个写入操作限定并且在两个写入操作之间没有中间写入操作的操作序列以及序列内的两个或更多个读取操作。从与中级语言规范中的操作相关联的依赖图和硬件组件生成流水线设计规范。对应于两个或多个读取操作的组件中的至少两个组件并行访问存储器，并且对应于两个或多个读取和两个写入操作的每个组件需要同步令牌作为输入，并且在完成时输出同步令牌操作。

9. 发明授权

US3936080A Pipeline expansion joint having a smooth bore 失效
标题翻译：管道膨胀节具有光滑的孔
公开(公告)号：US3936080A
公开(公告)日：1976-02-03
申请号：US474768
申请日：1974-05-30
申请人： David W. Bennett
发明人： David W. Bennett
IPC分类号： F16L51/00 , F16L55/00
CPC分类号： F16L51/00 , F16L55/00
摘要： A pipeline expansion joint having a smooth bore, for use with pipelines into which flow slurries containing solids in suspension, comprises a first sleeve open at both ends and having a tapered portion formed in the inner wall of one of its ends extending at a small angle with the axis of the first sleeve and over a substantial portion of the length of the first sleeve from its inside diameter to substantially its outside diameter, and a second sleeve also open at both ends and having a first portion of substantially the same inner diameter as the outer diameter of the first sleeve and telescopically mounted on the above-mentioned one end of the first sleeve, a second portion of the same diameter as the first sleeve, and an intermediate portion expanded at a small angle with the axis of the second sleeve over a substantial portion of its length from the second to the first portion of such second sleeve. The above expansion joint has a smooth bore throughout with no area of abrupt changes in order to prevent turbulence and the resulting wear due to the solids in suspension in the slurries.
摘要翻译：一种具有光滑孔的管道膨胀接头，用于与其中含有悬浮物中的固体的流动浆料的管道一起使用，其包括在两端开口的第一套筒，并且具有形成在其一端的内壁中的锥形部分，其以小角度延伸第一套筒的轴线和第一套筒的长度的大部分从其内径到其大致的外径，并且第二套筒也在两端开口，并且具有与第一套筒基本上相同的内径的第一部分第一套筒的外径和可伸缩地安装在第一套筒的上述一端上，与第一套筒直径相同的第二部分，以及与第二套筒的轴线成小角度膨胀的中间部分在其长度的大部分上从第二套筒的第二部分到第一部分。上述膨胀接头在没有突然变化的区域中具有光滑的孔，以防止由于浆料中的悬浮液中的固体而产生的湍流和由此产生的磨损。

10. 发明申请

US20110053336A1 METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：在半导体结构上选择性沉积介质层的方法
公开(公告)号：US20110053336A1
公开(公告)日：2011-03-03
申请号：US12553261
申请日：2009-09-03
申请人： Kiuchul Hwang , David W. Bennett , Huy Q. Nguyen
发明人： Kiuchul Hwang , David W. Bennett , Huy Q. Nguyen
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L21/8252 , H01L27/0605 , H01L28/40
摘要： A method for forming a capacitor and a transistor device on different surface portions of a semiconductor structure includes forming a passivation dielectric layer for the device; forming a bottom electrode for the capacitor; forming a removable layer extending over the bottom electrode and over the passivation dielectric layer with a window therein, such window exposing said bottom electrode; depositing a capacitor dielectric layer of the same or different material as the passivation dielectric layer over the removable layer with first portions passing through the window onto the exposed bottom electrode and second portions being over the removable layer, the thickness of the deposited layer being different from the thickness of the passivation layer; removing the removable layer with the second portions thereon while leaving said first portions on the bottom electrode; and forming a top electrode for the capacitor on the second portions remaining on the bottom electrode.
摘要翻译：一种用于在半导体结构的不同表面部分上形成电容器和晶体管器件的方法包括形成用于器件的钝化介质层; 形成电容器的底部电极; 形成在所述底部电极上延伸并且在所述钝化介电层上方具有窗口的可移除层，所述窗口暴露所述底部电极; 在可移除层上沉积与钝化介电层相同或不同的材料的电容器电介质层，其中第一部分通过窗口穿过暴露的底部电极，第二部分在可移除层之上，沉积层的厚度不同于钝化层的厚度; 在其上留下所述第一部分在底部电极上去除其上的第二部分的可移除层; 并且在残留在底部电极上的第二部分上形成用于电容器的顶部电极。

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