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1. 发明申请

US20120083117A1 Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer 有权
标题翻译：形成硬化多孔电介质层的方法和制造具有硬化多孔介电层的半导体器件的方法
公开(公告)号：US20120083117A1
公开(公告)日：2012-04-05
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/314 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

2. 发明授权

US09224593B2 Method of manufacturing a semiconductor device having a porous, low-k dielectric layer 有权
标题翻译：制造具有多孔低k电介质层的半导体器件的方法
公开(公告)号：US09224593B2
公开(公告)日：2015-12-29
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/312 , C25D1/08 , H01L21/02 , C23C16/40 , C23C16/56
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

3. 发明授权

US08524615B2 Method of forming hardened porous dielectric layer and method of fabricating semiconductor device having hardened porous dielectric layer 有权
标题翻译：形成硬化的多孔介电层的方法和制造具有硬化的多孔介电层的半导体器件的方法
公开(公告)号：US08524615B2
公开(公告)日：2013-09-03
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/469 , H01L21/31 , H01L21/44
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

4. 发明申请

US20120178253A1 Method of Manufacturing a Semiconductor Device Having a Porous, Low-K Dielectric Layer 有权
标题翻译：制造具有多孔低K电介质层的半导体器件的方法
公开(公告)号：US20120178253A1
公开(公告)日：2012-07-12
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

5. 发明授权

US08736018B2 Semiconductor devices and methods of manufacturing semiconductor devices 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US08736018B2
公开(公告)日：2014-05-27
申请号：US13314575
申请日：2011-12-08
申请人： Kyoung-Hee Kim , Gil-Heyun Choi , Kyu-Hee Han , Byung-Lyul Park , Byung-Hee Kim , Sang-Hoon Ahn , Kwang-Jin Moon
发明人： Kyoung-Hee Kim , Gil-Heyun Choi , Kyu-Hee Han , Byung-Lyul Park , Byung-Hee Kim , Sang-Hoon Ahn , Kwang-Jin Moon
IPC分类号： H01L21/764 , H01L21/00
CPC分类号： H01L21/76898 , H01L21/7682 , H01L21/76831 , H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13022 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48245 , H01L2224/48247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00013 , H01L2924/01327 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
摘要翻译：半导体器件包括具有第一触点的顶表面，具有第二触点的底表面，穿透基板的通孔，在通孔的侧壁上的绝缘层结构，其中具有气隙的绝缘层结构，所述贯通电极在所述绝缘层结构上具有上表面和下表面，所述贯通电极填充所述通孔，所述下表面是所述第二接触，以及金属布线，电连接到所述通孔的上表面，并电连接到第一次接触。

6. 发明申请

US20110263117A1 APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于制造半导体器件的装置及使用其制造半导体器件的方法
公开(公告)号：US20110263117A1
公开(公告)日：2011-10-27
申请号：US13094342
申请日：2011-04-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Byung-Hee Kim , Kyu-Hee Han
发明人： Sang-Don Nam , Sang-Hoon Ahn , Byung-Hee Kim , Kyu-Hee Han
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/2686 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/7684 , H01L21/76886 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture.
摘要翻译：制造半导体器件的方法和用于制造在化学机械抛光（CMP）工艺之后从多孔低电介质层去除水分的半导体器件的设备包括在衬底上形成多孔低电介质层。在具有多孔低电介质层的基板上形成金属互连。金属互连形成具有多孔低介电层的平坦表面以填充开口。将紫外（UV）光照射到多孔低电介质层，以从多孔低介电层去除吸收的水分。在具有多孔低电介质层和金属互连的基板上形成覆盖层。封盖层原位形成以防止额外吸收水分。

7. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

8. 发明授权

US06787468B2 Method of fabricating metal lines in a semiconductor device 有权
标题翻译：在半导体器件中制造金属线的方法
公开(公告)号：US06787468B2
公开(公告)日：2004-09-07
申请号：US10035257
申请日：2002-01-04
申请人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Gil-Heyun Choi
发明人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Gil-Heyun Choi
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76882 , H01L2221/1089
摘要： A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.
摘要翻译：一种制造在硅衬底上的绝缘层中具有凹陷区域的半导体器件的方法，包括以下步骤：在包括凹陷区域中的衬底表面的绝缘层的整个表面上沉积阻挡金属，在凹陷区域之外的阻挡金属上的成核层，在凹陷区域中的阻挡金属上沉积CVD-Al层，在抗成核层和除了在...中形成的阻挡金属之外沉积抑制铝迁移的金属或金属合金并且沉积PVD-Al层并再次流动PVD-Al层，以改善铝槽的质量。本方法抑制PVD-Al迁移和晶粒生长，这导致防止半导体器件中的异常图案化。

9. 发明申请

US20090315091A1 GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE 有权
标题翻译：门结构和具有门结构的半导体器件
公开(公告)号：US20090315091A1
公开(公告)日：2009-12-24
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L29/49 , H01L27/10
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

10. 发明申请

US20110092060A1 METHODS OF FORMING WIRING STRUCTURES 有权
标题翻译：形成接线结构的方法
公开(公告)号：US20110092060A1
公开(公告)日：2011-04-21
申请号：US12836081
申请日：2010-07-14
申请人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
发明人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L29/66621 , H01L21/76831 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/4236 , H01L29/665 , H01L29/78
摘要： A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
摘要翻译：一种半导体存储器布线方法，包括：接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞，所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线，所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞，第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线，所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。

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