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    • 7. 发明申请
    • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20120171826A1
    • 2012-07-05
    • US13243147
    • 2011-09-23
    • Jin-Bum KimChul-Sung KimYu-Gyun ShinDae-Yong KimJoon-Gon LeeKwang-Young Lee
    • Jin-Bum KimChul-Sung KimYu-Gyun ShinDae-Yong KimJoon-Gon LeeKwang-Young Lee
    • H01L21/8238
    • H01L21/823807H01L21/823814
    • A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
    • 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底,在第一区域中形成第一栅极和第一源极和漏极区域,并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层,在所述第一源极和漏极区域中形成第一金属硅化物层,在所述第一区域和所述第二区域上形成层间电介质层,形成多个接触孔, 第一金属硅化物层和外延层,同时穿透层间电介质层,在暴露的外延层中形成第二金属硅化物层,并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。
    • 8. 发明授权
    • Flash memory device and method of testing the flash memory device
    • 闪存设备和测试闪存设备的方法
    • US08149621B2
    • 2012-04-03
    • US12585725
    • 2009-09-23
    • Bo-geun KimDae-yong KimJun-yong Park
    • Bo-geun KimDae-yong KimJun-yong Park
    • G11C11/34
    • G11C29/12G11C16/04G11C2029/1208
    • A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
    • 提供一种闪存设备和测试闪存设备的方法。 闪存器件可以包括包括多个位线的存储单元阵列,被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。 多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一,并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据,将读出的测试数据与 估计数据,以确定对应的位线是否处于通过或故障状态,并输出测试结果信号。 如果第一页中的相应位线处于故障状态,则读取存储单元阵列的第二页的测试数据时,维持测试结果信号的电压。