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1. 发明专利

AU5680798A Vending machine displaying the on-line information and the digital video images 未知
公开(公告)号：AU5680798A
公开(公告)日：1999-06-28
申请号：AU5680798
申请日：1998-01-09
申请人： BYUNG HEE KIM , YOUNG HUN CHUNG
发明人： KIM BYUNG HEE , CHUNG YOUNG HUN
IPC分类号： G07F5/18 , G07F9/02 , G09F27/00 , H04L29/06 , H04N7/18 , G06F17/60 , G06F19/00
摘要： The present invention relates to a vending machine displaying the on-line information and the digital video images. This machine can receive various advertisement and information from the host network and display them on the attached monitor. The present invention includes: a vending machine part (200) includes a microprocessor (201) transmitting the product sales information signal to the communication interface (205), a communication interface (205) transmitting the product sales data to the communication interface (101) of the video processing part (100); a video processing part (100) loading the corresponding VGA and MPEC files to the product sales information saved in the external memory (107) after receiving the product sales information from the above vending machine part (200), and displaying those files using the multi-video device (108) after receiving the VGA and MPEC files from the computer network.

2. 发明申请

US20160141246A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160141246A1
公开(公告)日：2016-05-19
申请号：US14924217
申请日：2015-10-27
申请人： Jin-Nam Kim , Tsukasa Matsuda , Rak-Hwan Kim , Byung-Hee Kim , Nae-In Lee , Jong-Jin Lee
发明人： Jin-Nam Kim , Tsukasa Matsuda , Rak-Hwan Kim , Byung-Hee Kim , Nae-In Lee , Jong-Jin Lee
IPC分类号： H01L23/522
CPC分类号： H01L23/485 , H01L21/7684 , H01L21/76846 , H01L21/76849 , H01L21/76882 , H01L23/49822 , H01L23/49866 , H01L23/5226 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：第一层间绝缘层，包括第一沟槽，在衬底上，沿着侧壁形成的第一衬里层和第一沟槽的底表面，并且包括贵金属，贵金属属于第五周期之一，是国际纯粹和应用化学联合会（IUPAC）编号之后的第六周期，属于周期图的第八至第十组之一，以及填充第一衬里层上的第一沟槽的第一金属线，所述第一金属线的顶表面朝向所述第一沟槽的底表面具有凸形形状。

3. 发明申请

US20140273432A1 FABRICATING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20140273432A1
公开(公告)日：2014-09-18
申请号：US13841132
申请日：2013-03-15
申请人： BYUNG-HEE KIM , Tae-Soo Kim , Seong-Ho Park , Young-Ju Park , Ju-Young Jung
发明人： BYUNG-HEE KIM , Tae-Soo Kim , Seong-Ho Park , Young-Ju Park , Ju-Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/31144
摘要： A semiconductor device is fabricated by forming a lower conductor in a first interlayer dielectric film. A second interlayer dielectric film is formed on the lower conductor and the first interlayer dielectric film. A first hard mask pattern is formed on the second interlayer dielectric film. The first mask pattern has a first opening extending in a first direction. A planarization layer is formed on the first hard mask pattern. A mask pattern is formed on the planarization layer. The mask pattern has a second opening extending in a second direction perpendicular to the first direction. The lower conductor is positioned under an region where the first opening and the second opening overlap. A via hole and a trench connected to the via hole is formed using the first hard mask pattern and the mask pattern. The via hole exposes an upper surface of the lower conductor.
摘要翻译：通过在第一层间电介质膜中形成下导体来制造半导体器件。第二层间电介质膜形成在下导体和第一层间电介质膜上。在第二层间电介质膜上形成第一硬掩模图案。第一掩模图案具有沿第一方向延伸的第一开口。在第一硬掩模图案上形成平坦化层。在平坦化层上形成掩模图案。掩模图案具有沿垂直于第一方向的第二方向延伸的第二开口。下导体位于第一开口和第二开口重叠的区域的下方。使用第一硬掩模图案和掩模图案形成通孔和连接到通孔的沟槽。通孔露出下导体的上表面。

4. 发明授权

US08501606B2 Methods of forming wiring structures 有权
标题翻译：形成布线结构的方法
公开(公告)号：US08501606B2
公开(公告)日：2013-08-06
申请号：US12836081
申请日：2010-07-14
申请人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
发明人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66621 , H01L21/76831 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/4236 , H01L29/665 , H01L29/78
摘要： A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
摘要翻译：一种半导体存储器布线方法，包括：接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞，所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线，所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞，第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线，所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。

5. 发明授权

US08404576B2 Methods of forming a gate structure 有权
标题翻译：形成栅极结构的方法
公开(公告)号：US08404576B2
公开(公告)日：2013-03-26
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/283
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散减少层图案，其上的非晶层图案扩散减少层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

6. 发明申请

US20120178253A1 Method of Manufacturing a Semiconductor Device Having a Porous, Low-K Dielectric Layer 有权
标题翻译：制造具有多孔低K电介质层的半导体器件的方法
公开(公告)号：US20120178253A1
公开(公告)日：2012-07-12
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

7. 发明申请

US20120153500A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120153500A1
公开(公告)日：2012-06-21
申请号：US13314575
申请日：2011-12-08
申请人： Kyoung-Hee KIM , Gil-Heyun CHOI , Kyu-Hee HAN , Byung-Lyul PARK , Byung-Hee KIM , Sang-Hoon AHN , Kwang-Jin MOON
发明人： Kyoung-Hee KIM , Gil-Heyun CHOI , Kyu-Hee HAN , Byung-Lyul PARK , Byung-Hee KIM , Sang-Hoon AHN , Kwang-Jin MOON
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/7682 , H01L21/76831 , H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13022 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48245 , H01L2224/48247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00013 , H01L2924/01327 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
摘要翻译：半导体器件包括具有第一触点的顶表面，具有第二触点的底表面，穿透基板的通孔，在通孔的侧壁上的绝缘层结构，其中具有气隙的绝缘层结构，所述贯通电极在所述绝缘层结构上具有上表面和下表面，所述贯通电极填充所述通孔，所述下表面是所述第二接触，以及金属布线，电连接到所述通孔的上表面，并电连接到第一次接触。

8. 发明申请

US20120094437A1 METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL 有权
标题翻译：使用低K电介质材料的半导体器件通过硅形成的方法
公开(公告)号：US20120094437A1
公开(公告)日：2012-04-19
申请号：US13235717
申请日：2011-09-19
申请人： Kyu-hee Han , Sang-hoon Ahn , Jang-hee Lee , Jong-min Baek , Kyoung-hee Kim , Byung-lyul Park , Byung-hee Kim
发明人： Kyu-hee Han , Sang-hoon Ahn , Jang-hee Lee , Jong-min Baek , Kyoung-hee Kim , Byung-lyul Park , Byung-hee Kim
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76801 , H01L21/76825 , H01L21/76831 , H01L21/76898 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16146 , H01L2924/00014 , H01L2224/05552
摘要： A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
摘要翻译：通过硅通孔（TSV）形成的方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k介电材料，通过蚀刻主通孔中的低k电介质形成次级通孔以同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

9. 发明授权

US07998810B2 Methods of forming integrated circuit devices having stacked gate electrodes 有权
标题翻译：形成具有层叠栅电极的集成电路器件的方法
公开(公告)号：US07998810B2
公开(公告)日：2011-08-16
申请号：US12424922
申请日：2009-04-16
申请人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66545
摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
摘要翻译：提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

10. 发明授权

US07968410B2 Method of fabricating a semiconductor device using a full silicidation process 有权
标题翻译：使用全硅化工艺制造半导体器件的方法
公开(公告)号：US07968410B2
公开(公告)日：2011-06-28
申请号：US12460945
申请日：2009-07-27
申请人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
发明人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28123 , H01L21/28282
摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
摘要翻译：一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

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