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1. 发明授权

US08524615B2 Method of forming hardened porous dielectric layer and method of fabricating semiconductor device having hardened porous dielectric layer 有权
标题翻译：形成硬化的多孔介电层的方法和制造具有硬化的多孔介电层的半导体器件的方法
公开(公告)号：US08524615B2
公开(公告)日：2013-09-03
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/469 , H01L21/31 , H01L21/44
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

2. 发明申请

US20120083117A1 Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer 有权
标题翻译：形成硬化多孔电介质层的方法和制造具有硬化多孔介电层的半导体器件的方法
公开(公告)号：US20120083117A1
公开(公告)日：2012-04-05
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/314 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

3. 发明申请

US20120178253A1 Method of Manufacturing a Semiconductor Device Having a Porous, Low-K Dielectric Layer 有权
标题翻译：制造具有多孔低K电介质层的半导体器件的方法
公开(公告)号：US20120178253A1
公开(公告)日：2012-07-12
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

4. 发明授权

US09224593B2 Method of manufacturing a semiconductor device having a porous, low-k dielectric layer 有权
标题翻译：制造具有多孔低k电介质层的半导体器件的方法
公开(公告)号：US09224593B2
公开(公告)日：2015-12-29
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/312 , C25D1/08 , H01L21/02 , C23C16/40 , C23C16/56
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

5. 发明授权

US08404579B2 Methods of forming integrated circuit devices with crack-resistant fuse structures 有权
标题翻译：形成具有抗裂熔断结构的集成电路器件的方法
公开(公告)号：US08404579B2
公开(公告)日：2013-03-26
申请号：US12960150
申请日：2010-12-03
申请人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
发明人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.
摘要翻译：在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。在沟槽中形成熔丝。保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

6. 发明申请

US20110136332A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES 有权
标题翻译：形成集成电路设备的方法，具有抗电弧保险丝结构
公开(公告)号：US20110136332A1
公开(公告)日：2011-06-09
申请号：US12960150
申请日：2010-12-03
申请人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
发明人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.
摘要翻译：在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。在沟槽中形成熔丝。保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

7. 发明申请

US20110263117A1 APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于制造半导体器件的装置及使用其制造半导体器件的方法
公开(公告)号：US20110263117A1
公开(公告)日：2011-10-27
申请号：US13094342
申请日：2011-04-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Byung-Hee Kim , Kyu-Hee Han
发明人： Sang-Don Nam , Sang-Hoon Ahn , Byung-Hee Kim , Kyu-Hee Han
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/2686 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/7684 , H01L21/76886 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture.
摘要翻译：制造半导体器件的方法和用于制造在化学机械抛光（CMP）工艺之后从多孔低电介质层去除水分的半导体器件的设备包括在衬底上形成多孔低电介质层。在具有多孔低电介质层的基板上形成金属互连。金属互连形成具有多孔低介电层的平坦表面以填充开口。将紫外（UV）光照射到多孔低电介质层，以从多孔低介电层去除吸收的水分。在具有多孔低电介质层和金属互连的基板上形成覆盖层。封盖层原位形成以防止额外吸收水分。

8. 发明授权

US08298910B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08298910B2
公开(公告)日：2012-10-30
申请号：US12732907
申请日：2010-03-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
发明人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/3105 , H01L21/31144 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.
摘要翻译：提供一种制造半导体器件的方法，包括在第一和第二互连之间形成包括第一和第二互连的互连结构和绝缘材料，在互连上依次形成具有多个微孔的第一掩模层和第二掩模层结构，将第二掩模层中的多个微孔彼此聚结并在第二掩模层中形成多个第一微孔，在第一掩模层中使用多个第一微孔形成多个第二微孔，并且去除绝缘使用具有多个第二微孔的第一掩模层作为蚀刻掩模的材料，以便在第一和第二互连之间形成气隙。

9. 发明申请

US20100248471A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100248471A1
公开(公告)日：2010-09-30
申请号：US12732907
申请日：2010-03-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
发明人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/3105 , H01L21/31144 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.
摘要翻译：提供一种制造半导体器件的方法，包括在第一和第二互连之间形成包括第一和第二互连的互连结构和绝缘材料，在互连上依次形成具有多个微孔的第一掩模层和第二掩模层结构，将第二掩模层中的多个微孔彼此聚结并在第二掩模层中形成多个第一微孔，在第一掩模层中使用多个第一微孔形成多个第二微孔，并且去除绝缘使用具有多个第二微孔的第一掩模层作为蚀刻掩模的材料，以便在第一和第二互连之间形成气隙。

10. 发明授权

US07285810B2 Ferroelectric memory devices having expanded plate lines 有权
标题翻译：具有扩展板线的铁电存储器件
公开(公告)号：US07285810B2
公开(公告)日：2007-10-23
申请号：US10948610
申请日：2004-09-23
申请人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
发明人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
IPC分类号： H01L31/0224
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.
摘要翻译：铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，其被布置为在行和列方向上的多个行和列。多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过绝缘层中的开口。在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。相邻行中的铁电电容器可以共享公共铁电电介质区域。讨论相关的制造方法。

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