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1. 发明申请

US20050064820A1 Network analyzing method and apparatus for optimal performance of network, and a recording medium having programs to conduct said method 有权
标题翻译：用于网络的最佳性能的网络分析方法和装置，以及具有执行所述方法的程序的记录介质
公开(公告)号：US20050064820A1
公开(公告)日：2005-03-24
申请号：US10496782
申请日：2002-12-06
申请人： Sang Park , Yong Lee , Chi Ahn , Se Jung Lee , Bok Cheol Shin , Byeong Ahn , Jong Ihm
发明人： Sang Park , Yong Lee , Chi Ahn , Se Jung Lee , Bok Cheol Shin , Byeong Ahn , Jong Ihm
IPC分类号： H04L12/24 , H04B7/26 , H04W24/00 , H04B17/00
CPC分类号： H04W24/00
摘要： The present invention relates to method and apparatus of analyzing a wired/wireless communication network to optimize performance of the network. In the present invention, data are continuously gathered from all elements constituting a wired/wireless communication network and are analyzed to find an element of which performance and/or efficiency deteriorates. If found, an optimal plan to resolve low performance and/or efficiency is chosen through the data analysis and is then provided in real time. The present invention also relates to a recording medium storing computer programs to conduct said procedures.
摘要翻译：本发明涉及分析有线/无线通信网络以优化网络性能的方法和装置。在本发明中，从构成有线/无线通信网络的所有元件连续收集数据，并进行分析，以找出性能和/或效率恶化的元素。如果发现，通过数据分析选择解决低性能和/或效率的最佳方案，然后实时提供。本发明还涉及一种存储用于执行所述过程的计算机程序的记录介质。

2. 发明申请

US20060033184A1 Process and lead frame for making leadless semiconductor packages 有权
标题翻译：用于制造无引线半导体封装的工艺和引线框架
公开(公告)号：US20060033184A1
公开(公告)日：2006-02-16
申请号：US10915326
申请日：2004-08-11
申请人： Hyung Park , Hyeong Kim , Sang Park , Yong Lee , Kyung Rho , Jun Yang , Jin Won
发明人： Hyung Park , Hyeong Kim , Sang Park , Yong Lee , Kyung Rho , Jun Yang , Jin Won
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/568 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
摘要翻译：公开了一种用于制造多个无引线封装的工艺。首先，将芯片附着在其上形成有第一金属层的引线框架上。引线框架的每个引线具有连接第一部分和第二部分的第一部分，第二部分和第三部分，其中第一金属层未设置在第三部分上。在进行引线接合步骤和封装步骤之后，选择性地将第二金属层电镀在引线的第一部分和第二部分以及从模制产品的底部露出的芯片焊盘。然后，选择性地蚀刻每个引线的第三部分，使得第一部分和第二部分彼此电隔离。最后，进行一个单独的步骤来完成这个过程。本发明还提供了一种新的引线框设计。

3. 发明申请

US20070023873A1 Package structure having recession portion on the surface thereof and method of making the same 审中-公开
标题翻译：其表面具有凹陷部分的封装结构及其制造方法
公开(公告)号：US20070023873A1
公开(公告)日：2007-02-01
申请号：US11474382
申请日：2006-06-26
申请人： Sang Park , Yong Lee , Jin Hong , Bae Kim , Song Kim
发明人： Sang Park , Yong Lee , Jin Hong , Bae Kim , Song Kim
IPC分类号： H01L23/495
CPC分类号： H01L23/24 , H01L23/49861 , H01L24/48 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/16151 , H01L2924/16195 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a method for making a package structure having recession portion on the surface thereof. The method comprises: (a) providing a lead frame having a plurality of package units, each package unit having a plurality of leads and a die paddle; (b) providing an upper mold and a lower mold for clamping the lead frame, wherein the upper mold and the protruding block of the lower mold clamp the first portions of the leads so as to prevent molding compound bleeding to the upper surfaces of the first portions during mold filling operation, for improving the product yield; (c) injecting a molding compound between the upper mold and the lower mold, and forming a plurality of accommodation spaces; (d) attaching a plurality of chips onto the die paddles; (e) electrically connecting the chips to the first portions of the leads; (f) sealing the accommodation spaces; and (g) segregating the package units.
摘要翻译：本发明涉及一种在其表面上制造具有凹陷部分的包装结构的方法。该方法包括：（a）提供具有多个封装单元的引线框架，每个封装单元具有多个引线和管芯焊盘; （b）提供用于夹紧引线框架的上模具和下模具，其中上模具和下模具的突出块夹住引线的第一部分，以防止模塑复合物渗透到第一注塑过程中的部分，用于提高产品的产量; （c）在上模和下模之间注入模塑料，并形成多个容纳空间; （d）将多个芯片附接到芯片上; （e）将芯片电连接到引线的第一部分; （f）密封住宿处所; 和（g）分离包装单元。

4. 发明申请

US20070093004A1 Method of manufacturing thin film transistor including ZnO thin layer 审中-公开
标题翻译：包括ZnO薄层的薄膜晶体管的制造方法
公开(公告)号：US20070093004A1
公开(公告)日：2007-04-26
申请号：US11488895
申请日：2006-07-19
申请人： Sang Park , Chi Hwang , Hye Chu , Jeong Lee , Jin Lee , Ho Kwack , Yong Lee , Seung Kang
发明人： Sang Park , Chi Hwang , Hye Chu , Jeong Lee , Jin Lee , Ho Kwack , Yong Lee , Seung Kang
IPC分类号： H01L21/84
CPC分类号： H01L29/7869
摘要： Provided is a method of manufacturing a thin film transistor (TFT) including a transparent ZnO thin layer that is formed at a low temperature by causing a surface chemical reaction between precursors containing elements constituting the ZnO thin layer. The method includes the steps of: depositing a gate metal layer on a substrate and forming a gate electrode using photolithography and selective etching processes; depositing a gate insulator on the substrate having the gate electrode; forming source and drain electrodes; and depositing a ZnO thin layer on the gate insulator using a surface chemical reaction between precursors containing elements constituting the ZnO thin layer.
摘要翻译：提供一种制造薄膜晶体管（TFT）的方法，该薄膜晶体管（TFT）包括通过在构成ZnO薄层的元件的前体之间引起表面化学反应而在低温下形成的透明ZnO薄层。该方法包括以下步骤：在衬底上沉积栅极金属层并使用光刻和选择性蚀刻工艺形成栅电极; 在具有栅电极的衬底上沉积栅极绝缘体; 形成源极和漏极; 以及使用包含构成ZnO薄层的元素的前体之间的表面化学反应在栅极绝缘体上沉积ZnO薄层。

5. 发明申请

US20200013096A1 Third-Party Service Portal-Initiated Garment Service Bag Issuance, Volumetrically-Standardized Pricing, and Matchmaking System for Professional Garment Cleaning 审中-公开
公开(公告)号：US20200013096A1
公开(公告)日：2020-01-09
申请号：US16029590
申请日：2018-07-07
申请人： Sang Park
发明人： Sang Park
IPC分类号： G06Q30/02 , G06K7/10
摘要： A novel electronic system for third-party service portal-initiated garment service bag creation, distribution, volumetrically-standardized pricing, and matchmaking of professional garment cleaning is disclosed. The novel electronic system physically issues and electronically tracks volumetrically-standardized online garment service bags that are shipped to potential customers, who can then utilize such service bags to load garments at volumetrically-standardized fees per service bag and transport to a plurality of independent local garment cleaning service providers subscribed to the third-party service portal. The novel electronic system also enables the plurality of independent local garment cleaning service providers to define and competitively offer garment cleaning service fees that are objectively price-comparable on a price-per-unit bag metric of laundry load due to the volumetric standardization and the pre-distribution of online garment service bags by the third-party service portal, even before the potential customers utilize such service bags to load and ship garments to garment cleaning service providers.

6. 发明授权

US07773402B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07773402B2
公开(公告)日：2010-08-10
申请号：US12483482
申请日：2009-06-12
申请人： Sang Park , Shin Ho Chu
发明人： Sang Park , Shin Ho Chu
IPC分类号： G11C5/00 , G11C5/14 , G11C7/00
CPC分类号： G11C5/145 , H01L25/0657 , H01L2224/48225 , H01L2224/48227 , H01L2225/06568 , H01L2924/15311
摘要： A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.
摘要翻译：响应于自刷新和有效信号，第一信号输入电路输出第一控制信号。第二信号输入电路响应于自刷新和有效信号而输出第二控制信号。电源电路响应于第一控制信号向输出端施加第一电源电压。升高的电压发生器通过泵浦第二电源电压产生升高的电压，并且响应于第一和第二控制信号将升高的电压施加到输出端子。

7. 发明申请

US20080052868A1 Vacuum Cleaner 有权
标题翻译：吸尘器
公开(公告)号：US20080052868A1
公开(公告)日：2008-03-06
申请号：US11929271
申请日：2007-10-30
申请人： Jae Lee , Hyuk Kwon , Seog Kim , Sang Park
发明人： Jae Lee , Hyuk Kwon , Seog Kim , Sang Park
IPC分类号： A47L5/00
CPC分类号： B04C5/185 , A47L9/108 , A47L9/1608 , A47L9/165 , A47L9/1658 , A47L9/1666 , A47L9/1683 , A47L9/1691 , Y10S15/08 , Y10S55/03
摘要： There is provided a vacuum cleaner. The vacuum cleaner includes a dust storing part; a compression passage connecting a motor generating a negative pressure to the dust storing part; a flow passage control unit that controls opening and closing of the compression passage; and a compression unit compressing dust stored in the dust storing part when the compression passage is opened.
摘要翻译：提供真空吸尘器。真空吸尘器包括一个除尘部分; 压缩通道，其将产生负压的电动机连接到所述除尘部分; 流路控制单元，其控制压缩通路的开闭; 以及压缩单元，当压缩通道打开时，压缩存储在灰尘存储部分中的灰尘。

8. 发明申请

US20070140853A1 Dovetail surface enhancement for durability 有权
标题翻译：燕尾表面增强耐久性
公开(公告)号：US20070140853A1
公开(公告)日：2007-06-21
申请号：US11314147
申请日：2005-12-21
申请人： Michael McCann , Sang Park
发明人： Michael McCann , Sang Park
IPC分类号： F01D11/00
CPC分类号： F01D5/3092 , C23C4/04 , C23C30/00 , F04D29/023 , F04D29/322 , F05D2220/326 , F05D2220/327 , F05D2230/90 , F05D2300/1723 , F05D2300/509 , F05D2300/611 , Y02T50/673 , Y10T29/49327 , Y10T29/49336
摘要： A gas turbine engine blade having a dovetail with an enhanced surface for durability is disclosed. The blade includes an airfoil section and a dovetail section disposed opposite the airfoil section. The dovetail section has an outer surface, at least a portion of which has residual compressive stresses resulting from a plurality of peening operations. The dovetail section also includes a copper-nickel-indium wear coating layer disposed over the outer surface having residual compressive stresses and a lubricant coating layer disposed over the copper-nickel-indium wear coating layer, wherein the lubricant coating layer is lead-free.
摘要翻译：公开了一种具有燕尾形的燃气涡轮发动机叶片，其具有增强的耐久性表面。叶片包括翼型部分和与翼型部分相对设置的燕尾部分。燕尾部分具有外表面，其至少一部分具有由多个喷丸操作产生的残余压应力。燕尾部分还包括设置在具有残余压缩应力的外表面上的铜镍铟耐磨涂层和设置在铜 - 镍 - 铟耐磨涂层上的润滑剂涂层，其中润滑剂涂层是无铅的。

9. 发明申请

US20070119498A1 Electrode for solar cells, manufacturing method thereof and solar cell comprising the same 审中-公开
标题翻译：太阳能电池用电极及其制造方法以及包含该电极的太阳能电池
公开(公告)号：US20070119498A1
公开(公告)日：2007-05-31
申请号：US11485906
申请日：2006-07-13
申请人： Young Park , Jung Nam , Sang Park , Won Jung , Byung Sohn , Eun Lee
发明人： Young Park , Jung Nam , Sang Park , Won Jung , Byung Sohn , Eun Lee
IPC分类号： H01L31/00
CPC分类号： H01G9/2022 , Y02E10/542 , Y02P70/521
摘要： Disclosed herein is an electrode that includes a catalytic layer formed on a substrate coated with a conductive material, wherein the catalytic layer includes vertically aligned carbon nanotubes. A method of manufacturing the electrode and a solar cell comprising the electrode are also described. The electrode has increased surface roughness and a shortened charge transport pathway and, therefore, reduced charge transport resistance. Thus, when the electrode is used in a solar cell, it can improve the efficiency of the solar cell.
摘要翻译：本文公开了一种电极，其包括形成在涂覆有导电材料的基板上的催化层，其中催化层包括垂直排列的碳纳米管。还描述了制造电极的方法和包括电极的太阳能电池。电极具有增加的表面粗糙度和较短的电荷传输途径，因此降低了电荷传输电阻。因此，当电极用于太阳能电池中时，可以提高太阳能电池的效率。

10. 发明申请

US20070109717A1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US20070109717A1
公开(公告)日：2007-05-17
申请号：US11598672
申请日：2006-11-14
申请人： Byoung Lee , Hae Chung , Dong Park , Min Park , Sang Park , Sung Wi
发明人： Byoung Lee , Hae Chung , Dong Park , Min Park , Sang Park , Sung Wi
IPC分类号： H01G4/005
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.
摘要翻译：多层片状电容器包括具有电介质层的电容器主体，以及通过电介质层在电容器主体中彼此分离的内部电极层。每个内部电极层具有一个或两个引线并且包括至少一个共面电极板。外部电极通过引线电连接到内部电极层。内部电极层构成反复堆叠的多个块。每个块包括依次层叠的多个内部电极层。延伸到电容器主体的表面的引线沿堆叠方向布置成Z字形。具有相反极性的垂直相邻电极板的引线被布置成水平相邻。

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