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1. 发明授权

US07773402B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07773402B2
公开(公告)日：2010-08-10
申请号：US12483482
申请日：2009-06-12
申请人： Sang Park , Shin Ho Chu
发明人： Sang Park , Shin Ho Chu
IPC分类号： G11C5/00 , G11C5/14 , G11C7/00
CPC分类号： G11C5/145 , H01L25/0657 , H01L2224/48225 , H01L2224/48227 , H01L2225/06568 , H01L2924/15311
摘要： A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.
摘要翻译：响应于自刷新和有效信号，第一信号输入电路输出第一控制信号。第二信号输入电路响应于自刷新和有效信号而输出第二控制信号。电源电路响应于第一控制信号向输出端施加第一电源电压。升高的电压发生器通过泵浦第二电源电压产生升高的电压，并且响应于第一和第二控制信号将升高的电压施加到输出端子。

2. 发明授权

US08588013B2 Address decoding method and semiconductor memory device using the same 有权
标题翻译：地址解码方法及使用其的半导体存储器件
公开(公告)号：US08588013B2
公开(公告)日：2013-11-19
申请号：US13336840
申请日：2011-12-23
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C29/1201 , G11C29/12015 , G11C29/18
摘要： A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.
摘要翻译：半导体存储器件包括：选通时钟发生器，被配置为产生具有根据多个测试模式信号控制的延迟时间的选通时钟信号，所述测试模式信号响应于读取信号或写入信号被选择性地使能; 内部地址发生器，被配置为响应于所述选通时钟信号的第一电平来锁存地址，并且响应于所述选通时钟信号的第二电平对所述地址进行解码来产生内部地址; 以及输出使能信号发生器，被配置为对内部地址进行解码并产生有选择地使能的输出使能信号。

3. 发明申请

US20090168840A1 Thermal data output circuit and multi chip package using the same 有权
标题翻译：热数据输出电路和多芯片封装使用相同
公开(公告)号：US20090168840A1
公开(公告)日：2009-07-02
申请号：US12317218
申请日：2008-12-18
申请人： Ho Uk Song , Shin Ho Chu
发明人： Ho Uk Song , Shin Ho Chu
IPC分类号： G01K7/00
CPC分类号： G01K3/005
摘要： A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.
摘要翻译：提供温度数据输出电路，其能够输出当安装在多芯片封装上的至少一个半导体存储器芯片的内部温度超过预定温度时使能的温度信号。

4. 发明申请

US20090059691A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF 审中-公开
标题翻译：半导体集成电路及其多种测试方法
公开(公告)号：US20090059691A1
公开(公告)日：2009-03-05
申请号：US12169594
申请日：2008-07-08
申请人： Shin Ho Chu , Jong Won Lee
发明人： Shin Ho Chu , Jong Won Lee
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/18 , G11C2029/1202 , G11C2029/1204 , G11C2029/2602
摘要： A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi mat selection signals corresponding to one of the up mats and one of the down mats according to row addresses in an active operation mode, and a mat control section that receives the up and down mat input/output switch control signals and the multi mat selection signals and enables word lines and input/output switches in the mats corresponding to the signals.
摘要翻译：半导体集成电路包括多模式控制信号产生部分，其能够在读操作模式期间根据上/下信息地址使得上和下输入/输出开关控制信号之一用于根据上/下信息地址来控制上/下按钮中的输入/输出开关，多模式解码部分，其根据活动操作模式中的行地址同时激活对应于上层和下层之一的多层选择信号;以及垫控制部分，其接收上和下垫输入 /输出开关控制信号和多功能席选择信号，并使得字符线和输入/输出开关在与信号相对应的垫中。

5. 发明申请

US20080123460A1 Deep power down mode control circuit 有权
标题翻译：深度掉电模式控制电路
公开(公告)号：US20080123460A1
公开(公告)日：2008-05-29
申请号：US11811863
申请日：2007-06-11
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/144
摘要： A deep power down mode control circuit is disclosed. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.
摘要翻译：公开了一种深度掉电模式控制电路。深度掉电模式控制电路包括深度掉电信号发生器，用于响应于突发命令信号和时钟使能信号输出深度掉电信号，以及深度掉电延迟控制器，用于将深度掉电信号延迟用于预定的延迟时间，并输出延迟的信号。

6. 发明授权

US07902902B2 Anti-fuse repair control circuit for preventing stress on circuit parts 失效
标题翻译：防熔丝修复控制电路，用于防止电路部件的应力
公开(公告)号：US07902902B2
公开(公告)日：2011-03-08
申请号：US11964294
申请日：2007-12-26
申请人： Shin Ho Chu , Min Jung Koh
发明人： Shin Ho Chu , Min Jung Koh
IPC分类号： H01H85/00
CPC分类号： G11C17/18
摘要： The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
摘要翻译：本发明涉及一种反熔丝修复控制电路，其调节电源电压和反向偏置电压的传输，所述反向偏置电压被转换为修复反熔丝到电路部分。因此，本发明在抗熔丝修复期间防止高功率电压或低背偏压对诸如电池，外围电路或芯区域的电路部分的影响。反熔丝修复控制电路包括反熔丝修复使能部件，其提供对应于抗熔丝修复的抗熔丝修复使能信号; 电源电压控制部，根据所述反熔丝修复使能信号的使能状态，控制向第一电路部的电力电压的传输; 以及反偏压控制部，其根据反熔丝修复使能信号的使能状态来控制向第二电路部的透射。

7. 发明授权

US07800431B2 Internal voltage generation circuit 有权
标题翻译：内部电压产生电路
公开(公告)号：US07800431B2
公开(公告)日：2010-09-21
申请号：US11821600
申请日：2007-06-25
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G05F1/465 , G11C5/144
摘要： Various examples of internal voltage generation circuit are provided. In one example, the internal voltage generation circuit includes a level control signal generator for generating a level control signal in response to a power down mode signal, which is activated synchronously with a clock enable signal, and a precharge flag signal, which is enabled when a precharge operation, is performed, and an internal voltage generator for generating an internal voltage in response to the level control signal and outputting it to an output node.
摘要翻译：提供内部电压产生电路的各种示例。在一个示例中，内部电压产生电路包括电平控制信号发生器，用于响应于与时钟使能信号同步激活的掉电模式信号和预充电标志信号产生电平控制信号，该预充电标志信号在执行预充电操作，以及内部电压发生器，用于响应于电平控制信号产生内部电压并将其输出到输出节点。

8. 发明申请

US20090134935A1 ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS 失效
标题翻译：用于防止电路部件应力的防熔丝维修控制电路
公开(公告)号：US20090134935A1
公开(公告)日：2009-05-28
申请号：US11964294
申请日：2007-12-26
申请人： Shin Ho Chu , Min Jung Koh
发明人： Shin Ho Chu , Min Jung Koh
IPC分类号： H01H85/00
CPC分类号： G11C17/18
摘要： The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
摘要翻译：本发明涉及一种反熔丝修复控制电路，其调节电源电压和反向偏置电压的传输，所述反向偏置电压被转换为修复反熔丝到电路部分。因此，本发明在抗熔丝修复期间防止高功率电压或低背偏压对诸如电池，外围电路或芯区域的电路部分的影响。反熔丝修复控制电路包括反熔丝修复使能部件，其提供对应于抗熔丝修复的抗熔丝修复使能信号; 电源电压控制部，根据所述反熔丝修复使能信号的使能状态，控制向第一电路部的电力电压的传输; 以及反偏压控制部，其根据反熔丝修复使能信号的使能状态来控制向第二电路部的透射。

9. 发明申请

US20070274146A1 TRAS adjusting circuit for self-refresh mode in a semiconductor device 有权
标题翻译：用于半导体器件中的自刷新模式的TRAS调整电路
公开(公告)号：US20070274146A1
公开(公告)日：2007-11-29
申请号：US11648270
申请日：2006-12-29
申请人： Mi Hyun Hwang , Shin Ho Chu
发明人： Mi Hyun Hwang , Shin Ho Chu
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A tRAS adjusting circuit extends an active operation in a self-refresh operation. The tRAS adjusting circuit includes: a self-refresh sensing unit for receiving a self-refresh signal and a refresh signal and generating a sensing signal; a first extension unit for extending an enable interval of an active operation pulse; a second extension unit for extending an enable interval of an output signal of the first extension unit; a transfer unit for transferring either the output signal of the first extension unit or an output signal of the second extension unit as a tRAS signal according to an enable state of the sensing signal; and an active signal output unit for receiving the active operation pulse and tRAS signal and outputting an enable state of the active operation pulse as an active signal until the tRAS signal is disabled.
摘要翻译： tRAS调整电路在自刷新操作中扩展了活动操作。 tRAS调整电路包括：自刷新感测单元，用于接收自刷新信号和刷新信号并产生感测信号; 第一扩展单元，用于延长有效操作脉冲的使能间隔; 第二扩展单元，用于扩展第一扩展单元的输出信号的使能间隔; 传送单元，用于根据感测信号的使能状态将第一扩展单元的输出信号或第二扩展单元的输出信号作为tRAS信号传送; 以及有源信号输出单元，用于接收有源操作脉冲和tRAS信号，并且将有效操作脉冲的使能状态作为有效信号输出，直到tRAS信号被禁止为止。

10. 发明授权

US09368237B2 Semiconductor integrated circuit capable of controlling test modes without stopping test 有权
标题翻译：半导体集成电路能够在不停止测试的情况下控制测试模式
公开(公告)号：US09368237B2
公开(公告)日：2016-06-14
申请号：US12483372
申请日：2009-06-12
申请人： Sun Mo An , Shin Ho Chu
发明人： Sun Mo An , Shin Ho Chu
IPC分类号： G11C29/46
CPC分类号： G11C29/46
摘要： A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
摘要翻译：提出了能够控制测试模式而不停止半导体集成电路测试的半导体集成电路。半导体集成电路包括：测试模式控制单元，被配置为响应于地址解码信号产生第一组的多个测试模式信号和第二组的多个测试模式信号。测试模式控制单元通过使用第二组的测试模式信号提供复位信号来选择性地使第一组的测试模式信号失效。因此，可以通过使用复位信号使先前的测试模式失效并且通过执行新的测试模式而不断开测试模式状态来减少半导体集成电路的测试时间。

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