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1. 发明专利

JP2007183941A Memory system capable of changing configuration of memory module 有权
标题翻译：可更改存储器模块配置的存储器系统
公开(公告)号：JP2007183941A
公开(公告)日：2007-07-19
申请号：JP2006348010
申请日：2006-12-25
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： RI SAISHUN , KIM JONG-HOON , PARK KWANG-SOO
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F13/1694
摘要： PROBLEM TO BE SOLVED: To provide a memory system capable of changing a configuration of a memory module.
SOLUTION: This memory system is provided with first, second, and third connectors arranged on a system board and a memory controller connected to a pin in the third connector via a channel. The third connector is provided with a pin connected to a pin in the first connector via the channel and a pin connected to a pin in the second connector via the channel. When the memory system has a first memory capacity, a dummy module is arranged in each of the first and second connectors. When the first memory module is mounted on the third connector, the dummy module and the first memory module are connected to the memory controller. When the memory system has a second memory capacity higher than the first memory capacity, the second memory modules are connected to the memory controller by installing the second memory modules in the first connector and the second connector alone.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够改变存储器模块的配置的存储器系统。解决方案：该存储器系统设置有布置在系统板上的第一，第二和第三连接器以及经由通道连接到第三连接器中的引脚的存储器控制器。第三连接器设置有经由通道连接到第一连接器中的引脚的引脚和经由通道连接到第二连接器中的引脚的引脚。当存储器系统具有第一存储器容量时，在第一和第二连接器的每一个中布置虚拟模块。当第一存储器模块安装在第三连接器上时，虚拟模块和第一存储器模块连接到存储器控制器。当存储器系统具有高于第一存储器容量的第二存储器容量时，通过将第二存储器模块安装在第一连接器和第二连接器中来将第二存储器模块连接到存储器控制器。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007207227A Memory system having improved multi-module memory bus structure 审中-公开
标题翻译：具有改进的多模块存储器总线结构的存储器系统
公开(公告)号：JP2007207227A
公开(公告)日：2007-08-16
申请号：JP2007000123
申请日：2007-01-04
申请人： Korea Advanced Inst Of Sci Technol , Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd. , 韓国科学技術院
发明人： SUNG MYUNG-HEE , KIM JONG-HOON , KIM JOUNG-HO , KIM JIN-GOOK
IPC分类号： G06F13/16 , G06F3/00 , G06F12/00
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14
摘要： PROBLEM TO BE SOLVED: To provide a memory system having a multi-module memory bus structure which can reduce or remove re-reflection through a transmission line by utilizing a Wilkinson power divider.
SOLUTION: The memory system includes: a memory controller; a transmission bus whose one end is connected to the memory controller for transmitting a signal; the power distributor whose first node is connected to the other end of the transmission bus and having second and third nodes; a first memory module connected to the second node through a first branch bus; and a second memory module connected to the third node through a second branch bus. Consequently, occurrence of interference in the signal transmission of the first memory module is prevented by allowing a signal reflected from the second memory module to generate resonance through the second branch bus by impedance mismatching.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有多模块存储器总线结构的存储器系统，其可以通过利用威尔金森功率分配器来减少或消除通过传输线的再反射。解决方案：存储器系统包括：存储器控制器; 传输总线，其一端连接到用于发送信号的存储器控制器; 所述电力分配器的第一节点连接到所述传输总线的另一端并且具有第二和第三节点; 通过第一分支总线连接到第二节点的第一存储器模块; 以及通过第二分支总线连接到第三节点的第二存储器模块。因此，通过允许从第二存储器模块反射的信号通过第二分支总线通过阻抗失配产生谐振来防止第一存储器模块的信号传输中的干扰的发生。版权所有（C）2007，JPO＆INPIT

3. 发明专利

DE602006019190D1 Schiebemodul für tragbares Endgerät 未知
公开(公告)号：DE602006019190D1
公开(公告)日：2011-02-10
申请号：DE602006019190
申请日：2006-07-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JEONG-SEOK , JUNG KWANG-HO , SEO KWANG-SU , KIM JONG-HOON
IPC分类号： H04M1/02

4. 发明专利

DE19748009A1 未知
公开(公告)号：DE19748009A1
公开(公告)日：1998-05-14
申请号：DE19748009
申请日：1997-10-30
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HWANG YEONG-GIL , KIM SOO-HYUN , KIM JONG-HOON
IPC分类号： G06F13/00 , G06F15/163 , H04L29/06 , H04L29/08
摘要： A computer network system includes a network program for establishing an inter-system communication between clients and the server by using a socket function. If a 'bind ( )' system call results in failure in the course of making the inter-system communication by using the socket function, the 'bind ( )' system call is retried after a lapse of a predetermined time. The predetermined time is a time determined based on a time delay in closing the abnormal socket.

5. 发明专利

DE19748009B4 未知
公开(公告)号：DE19748009B4
公开(公告)日：2008-09-25
申请号：DE19748009
申请日：1997-10-30
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HWANG YEONG-GIL , KIM SOO-HYUN , KIM JONG-HOON
IPC分类号： G06F13/00 , G06F15/163 , H04L1/08 , H04L29/06 , H04L29/08
摘要： A computer network system includes a network program for establishing an inter-system communication between clients and the server by using a socket function. If a 'bind ( )' system call results in failure in the course of making the inter-system communication by using the socket function, the 'bind ( )' system call is retried after a lapse of a predetermined time. The predetermined time is a time determined based on a time delay in closing the abnormal socket.

6. 发明专利

GB2319151A Retrying network socket after predetermined time 未知
公开(公告)号：GB2319151A
公开(公告)日：1998-05-13
申请号：GB9723131
申请日：1997-11-03
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HWANG YEONG-GILL , KIM SOO-HYUN , KIM JONG-HOON
IPC分类号： G06F15/163 , G06F13/00 , H04L29/06 , H04L29/08
摘要： A method and apparatus for assigning a socket in a network system is described. According to the method, if an attempt to assign a socket fails, another attempt is not made until a pre-determined time has elapsed.

7. 发明专利

DE102006062578B4 Speichersystem 未知
公开(公告)号：DE102006062578B4
公开(公告)日：2016-07-21
申请号：DE102006062578
申请日：2006-12-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE JAE-JUN , KIM JONG-HOON , PARK KWANG-SOO
IPC分类号： G11C5/06 , G06F13/16
摘要： Speichersystem (100) umfassend: – einen ersten, einen zweiten und einen dritten Konnektor (110, 120, 130), die auf einer Systemplatine angeordnet sind, wobei der dritte Konnektor (130) Anschlüsse (P3) umfasst, die mit Anschlüssen (P1, P2) des ersten und des zweiten Konnektors (110, 120) über Kanäle verbunden sind, und eine Speichersteuereinheit (140), der über Kanäle mit den Anschlüssen (P3) des dritten Konnektors (130) verbunden ist, – wobei das Speichersystem (100), wenn es mit einer ersten Speicherkapazität konfiguriert ist, Dummy-Speichermodule (160) und ein erstes Speichermodul (150) umfasst, die durch Installieren der Dummy-Speichermodule (160) in den ersten und den zweiten Konnektor (110, 120) und durch Installieren des ersten Speichermoduls (150) in den dritten Konnektor (130) mit der Speichersteuereinheit (140) verbunden sind, und – wobei das Speichersystem (100), wenn es alternativ mit einer zweiten Speicherkapazität konfiguriert ist, die größer als die erste Speicherkapazität ist, zweite Speichermodule (170) umfasst, die durch Installieren der zweiten Speichermodule (170) nur in den ersten und den zweiten Konnektor (110, 120) mit der Speichersteuereinheit (140) verbunden sind.

8. 发明专利

DE102007006283A1 未知
公开(公告)号：DE102007006283A1
公开(公告)日：2007-08-30
申请号：DE102007006283
申请日：2007-02-01
申请人： KOREA ADVANCED INST SCI & TECH , SAMSUNG ELECTRONICS CO LTD
发明人： SUNG MYUNG-HEE , KIM JONG-HOON , KIM JIN-GOOK , KIM JOUNG-HO
IPC分类号： G11C5/06
摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

9. 发明专利

DE102006062578A1 未知
公开(公告)号：DE102006062578A1
公开(公告)日：2007-07-26
申请号：DE102006062578
申请日：2006-12-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE JAE-JUN , KIM JONG-HOON , PARK KWANG-SOO
IPC分类号： G11C5/06
摘要： A memory system is disclosed with first, second, and third connectors located on a system board, the third connector including pins connected to the pins of the first and second connectors through channels, and a memory controller connected to the pins of the third connector through channels. The memory system, as configured in a first memory capacity, comprises; dummy memory modules and a first memory module connected to the memory controller by installing the dummy memory modules in the first and second connectors and installing the first memory module in the third connector. The memory system, as alternately configured in a second memory capacity larger than the first memory capacity, comprises second memory modules connected to the memory controller by installing the second memory modules in only the first and second connectors.

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