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1. 发明专利

DE102007006283A1 未知
公开(公告)号：DE102007006283A1
公开(公告)日：2007-08-30
申请号：DE102007006283
申请日：2007-02-01
申请人： KOREA ADVANCED INST SCI & TECH , SAMSUNG ELECTRONICS CO LTD
发明人： SUNG MYUNG-HEE , KIM JONG-HOON , KIM JIN-GOOK , KIM JOUNG-HO
IPC分类号： G11C5/06
摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

2. 发明专利

JP2007207227A Memory system having improved multi-module memory bus structure 审中-公开
标题翻译：具有改进的多模块存储器总线结构的存储器系统
公开(公告)号：JP2007207227A
公开(公告)日：2007-08-16
申请号：JP2007000123
申请日：2007-01-04
申请人： Korea Advanced Inst Of Sci Technol , Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd. , 韓国科学技術院
发明人： SUNG MYUNG-HEE , KIM JONG-HOON , KIM JOUNG-HO , KIM JIN-GOOK
IPC分类号： G06F13/16 , G06F3/00 , G06F12/00
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14
摘要： PROBLEM TO BE SOLVED: To provide a memory system having a multi-module memory bus structure which can reduce or remove re-reflection through a transmission line by utilizing a Wilkinson power divider.
SOLUTION: The memory system includes: a memory controller; a transmission bus whose one end is connected to the memory controller for transmitting a signal; the power distributor whose first node is connected to the other end of the transmission bus and having second and third nodes; a first memory module connected to the second node through a first branch bus; and a second memory module connected to the third node through a second branch bus. Consequently, occurrence of interference in the signal transmission of the first memory module is prevented by allowing a signal reflected from the second memory module to generate resonance through the second branch bus by impedance mismatching.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有多模块存储器总线结构的存储器系统，其可以通过利用威尔金森功率分配器来减少或消除通过传输线的再反射。解决方案：存储器系统包括：存储器控制器; 传输总线，其一端连接到用于发送信号的存储器控制器; 所述电力分配器的第一节点连接到所述传输总线的另一端并且具有第二和第三节点; 通过第一分支总线连接到第二节点的第一存储器模块; 以及通过第二分支总线连接到第三节点的第二存储器模块。因此，通过允许从第二存储器模块反射的信号通过第二分支总线通过阻抗失配产生谐振来防止第一存储器模块的信号传输中的干扰的发生。版权所有（C）2007，JPO＆INPIT

3. 发明专利

DE102007025775B4 未知
公开(公告)号：DE102007025775B4
公开(公告)日：2010-05-06
申请号：DE102007025775
申请日：2007-05-22
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SUNG MYUNG-HEE , AHN YOUNG-MAN
IPC分类号： H01L23/60 , H01L27/108
摘要： A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.

4. 发明专利

DE102007025775A1 未知
公开(公告)号：DE102007025775A1
公开(公告)日：2007-12-06
申请号：DE102007025775
申请日：2007-05-22
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SUNG MYUNG-HEE , AHN YOUNG-MAN
IPC分类号： H01L23/60 , H01L27/108
摘要： A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.

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