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    • 3. 发明专利
    • Impedance adjustment circuit, integrated circuit including the same and impedance adjustment method of output driver using the same
    • 阻抗调整电路,包括相同的集成电路和使用其的输出驱动器的阻抗调整方法
    • JP2006115489A
    • 2006-04-27
    • JP2005276474
    • 2005-09-22
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • CHUNG HOE-JULEE JAE-JUNKIM KYU-HYOUN
    • H03K19/0175H04L25/02
    • H04L25/0278
    • PROBLEM TO BE SOLVED: To provide an impedance calibration circuit, integrated circuit including the same, and impedance adjustment method of an output driver utilizing the same. SOLUTION: The present invention relates to an impedance adjustment circuit including a calibration circuit, a first register and a second register. The calibration circuit generates a reference current by supplying an internal voltage to an external resistor connected to a calibration terminal and outputs first and second calibration signals in response to the reference current, first and second reference voltages and first and second impedance control signals. The first register increases/decreases a bit value of the first impedance control signal in response to the first calibration signal. The second register increases/decreases a bit value of the second impedance control signal in response to the second calibration signal. Thus, the skew of a signal transmitted by the output driver can be decreased. COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:提供一种阻抗校准电路,包括该阻抗校准电路的集成电路和使用该阻抗校正电路的输出驱动器的阻抗调节方法。 阻抗调整电路技术领域本发明涉及一种包括校准电路,第一寄存器和第二寄存器的阻抗调整电路。 校准电路通过向连接到校准端子的外部电阻器提供内部电压来产生参考电流,并响应于参考电流,第一和第二参考电压以及第一和第二阻抗控制信号而输出第一和第二校准信号。 第一寄存器响应于第一校准信号增加/减少第一阻抗控制信号的位值。 第二寄存器响应于第二校准信号增加/减少第二阻抗控制信号的位值。 因此,可以减少由输出驱动器发送的信号的偏斜。 版权所有(C)2006,JPO&NCIPI
    • 10. 发明专利
    • Memory module and method of arranging signal line of same
    • 记忆模块及其信号线的安装方法
    • JP2005243028A
    • 2005-09-08
    • JP2005049383
    • 2005-02-24
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • YOON CHIL-NAMSO HEISELEE JUNG-JOONLEE JAE-JUNPARK YOUNG-JUNYU IL-SUNG
    • G06F12/00G11C5/06G11C11/401H05K1/18
    • G11C5/063H05K1/181H05K2201/09254Y02P70/611
    • PROBLEM TO BE SOLVED: To provide a memory module and a method of arranging a signal line of the memory module. SOLUTION: The method of arranging the signal line of the memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供一种存储模块和布置存储器模块的信号线的方法。 解决方案:布置存储器模块的信号线的方法包括:将多个存储器分类成包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点,并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点,以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点,接收外部信号,并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。 版权所有(C)2005,JPO&NCIPI