专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6157572A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US6157572A
公开(公告)日：2000-12-05
申请号：US85680
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生擦除脉冲的电源。控制器控制电源以将擦除脉冲施加到未被取消选择的所有字线。然后，按顺序对单元应用擦除验证程序。如果连接到字线的所有单元都通过擦除验证测试，则字线被取消选择，使得后续的擦除脉冲不会被施加到字线并且可能导致单元变得过高。在本发明的一个实施例中，在施加擦除脉冲之后对所有单元执行擦除验证。当所有单元通过擦除验证时，擦除操作完成。在另一实施例中，按顺序对每个单元施加擦除验证，其中施加擦除脉冲，直到每个当前单元通过擦除验证。字母可以单独或分组取消选择。本发明导致电池的阈值电压分布的紧缩。

2. 发明授权

US5901090A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US5901090A
公开(公告)日：1999-05-04
申请号：US85552
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个具有源极，漏极，浮动栅极和控制栅极的场效应晶体管存储单元，以及用于向单元提供多个电压的电源。控制器控制电源向单元施加至少一个擦除脉冲。然后，将至少一个过度校正或“软编程”脉冲施加到单元，在该单元期间，单元的源极，漏极和控制栅极电压使得过度流过的单元的阈值电压将增加，但是最小擦除的单元将不会被打扰过度校正脉冲从而使阈值电压分布紧密。在过渡期校正脉冲的持续时间内施加衬底偏置电压源，即使在具有低电源电压的应用中，也可以将电池的背景泄漏降低到可以有效执行过电压修正操作的水平。

3. 发明授权

US5875130A Method for programming flash electrically erasable programmable read-only memory 失效
标题翻译：闪存电可擦除可编程只读存储器的编程方法
公开(公告)号：US5875130A
公开(公告)日：1999-02-23
申请号：US085705
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
IPC分类号： G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值电池中的漏电流。操作脉冲可以是过高修正脉冲。在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。操作脉冲也可以是编程脉冲。在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

4. 发明授权

US06459625B1 Three metal process for optimizing layout density 有权
标题翻译：三金属工艺优化布局密度
公开(公告)号：US06459625B1
公开(公告)日：2002-10-01
申请号：US09767341
申请日：2001-01-23
申请人： Colin S. Bill , Jonathan S. Su , Ravi P. Gutala
发明人： Colin S. Bill , Jonathan S. Su , Ravi P. Gutala
IPC分类号： G11C1604
CPC分类号： G11C5/025 , G11C16/0408
摘要： The present invention discloses a method and system to optimize electrical interconnection of electrical components in a periphery area of a memory device thereby minimizing the periphery area. The periphery area is divided into a plurality of sub-circuits formed by selectively electrically connecting the electrical components. Electrical interconnection of the electrical components to form the sub-circuits is accomplished using a first metal layer and a second metal layer. The first metal layer is formed to create a plurality of first metal layer lines that are oriented to extend in substantially one direction on the memory device. The second metal layer is formed to create a plurality of second metal layer lines that are oriented to extend substantially perpendicular to the first metal layer lines. The plurality of sub-circuits are electrically interconnected using a third metal layer that is formed to create a plurality of third metal layer lines that are oriented to extend substantially parallel to the first metal layer lines.
摘要翻译：本发明公开了一种用于优化存储器件周边区域中的电气元件的电互连从而最小化外围区域的方法和系统。周边区域被分成通过选择性地电连接电气部件而形成的多个子电路。使用第一金属层和第二金属层实现电气部件的电互连以形成子电路。形成第一金属层以形成多个第一金属层线，其被定向成在存储器件上沿基本上一个方向延伸。形成第二金属层以形成多个第二金属层线，其被定向成基本上垂直于第一金属层线延伸。多个子电路使用第三金属层电互连，第三金属层被形成以形成多个第三金属层线，其被定向成基本上平行于第一金属层线延伸。

5. 发明授权

US6134146A Wordline driver for flash electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：用于闪存电子可擦除可编程只读存储器（EEPROM）的字线驱动程序
公开(公告)号：US6134146A
公开(公告)日：2000-10-17
申请号：US166385
申请日：1998-10-05
申请人： Colin S. Bill , Jonathan S. Su , Takao Akaogi , Ravi P. Gutala
发明人： Colin S. Bill , Jonathan S. Su , Takao Akaogi , Ravi P. Gutala
IPC分类号： G11C16/06 , G11C8/08 , G11C16/08 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power source for generating a low power supply voltage on the order of 3 V or less. A wordline driver includes a booster for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the beginning of the read operation to ensure that the cells have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生大约3V或更小的低电源电压的电源。字线驱动器包括用于升高电源电压的升压器，以产生高于电源电压的字线读取电压，并将字线电压施加到字线。上限钳位限制字线电压的最大值，以防止读取干扰。上夹具可以被配置为减小最大值随着电源电压而变化的量，或者将最大值限制为基本上预定值。在读取操作开始时，下限钳位将字线电压限制在比电源电压高并且低于预定时间长度的最小值的最小值，以确保单元具有足够的读取电流并且减少最小值随着电源电压而变化的量。

6. 发明授权

US06205059B1 Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US06205059B1
公开(公告)日：2001-03-20
申请号：US09166384
申请日：1998-10-05
申请人： Ravi P. Gutala , Jonathan S. Su , Colin S. Bill
发明人： Ravi P. Gutala , Jonathan S. Su , Colin S. Bill
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells, a power supply, and a controller which cooperates with the power supply to apply an erase pulse to the cells, and then erase verify a first byte of cells in each sector. If the first bytes in any sector has not passed erase verify, another erase pulse is applied to the cells of those sectors, and the first byte in each sector which did not pass erase verify the first time is erase verified again. This procedure is continued until the first byte in each sector has passed erase verify. Then, the sectors are processed in sequence to erase and erase verify every cell. First, an erase pulse is applied to all of the cells in the sector. Then, the first byte is erase verified. If the first byte passes erase verify (which it will because it did previously), the next byte is erase verified. Whenever a particular byte does not pass erase verify, another erase pulse is applied to all of the cells in the sector, and the particular cell is again erase verified. This procedure is sequentially performed on all of the bytes in the sector, or alternatively on the cells individually, until all of the cells have passed erase verify.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个场效应晶体管存储器单元，电源和与电源配合以向单元施加擦除脉冲的控制器，然后擦除验证每个扇区中单元格的第一个字节。如果任何扇区中的第一个字节没有通过擦除验证，则另一个擦除脉冲被施加到这些扇区的单元，而不通过擦除的每个扇区中的第一个字节在第一次再次被擦除验证。该过程继续，直到每个扇区中的第一个字节已经通过擦除验证。然后，扇区按顺序进行处理，以擦除和擦除每个单元的验证。首先，擦除脉冲被施加到扇区中的所有单元。然后，第一个字节被擦除验证。如果第一个字节通过擦除验证（由于之前已经执行了该验证），则下一个字节被擦除验证。每当特定字节不通过擦除验证时，另一个擦除脉冲被施加到扇区中的所有单元，并且特定单元被再次擦除验证。该过程顺序地在扇区中的所有字节上或者单独地在单元上执行，直到所有单元已经通过擦除验证。

7. 发明授权

US06430087B1 Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage 有权
标题翻译：用于字线增强器的修整方法和系统，以最大限度地减少提升字线电压的工艺变化
公开(公告)号：US06430087B1
公开(公告)日：2002-08-06
申请号：US09547660
申请日：2000-04-12
申请人： Colin S. Bill , Ravi P. Gutala
发明人： Colin S. Bill , Ravi P. Gutala
IPC分类号： G11C1600
CPC分类号： G11C16/08 , G11C5/145 , G11C8/08
摘要： A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster in a wordline voltage booster circuit. An adjustable clamp circuit is electrically connected with the wordline voltage booster circuit for clamping the gate voltage that is generated by the voltage booster at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit that is electrically connected to the adjustable clamp circuit, depending on process variations experienced during fabrication by the adjustable clamp circuit.
摘要翻译：通过本发明公开了一种用于控制在闪速存储器中的读取操作期间使用的升压的字线电压的方法和系统。在优选实施例中，栅极电压由字线升压电路中的升压器产生。可调式钳位电路与字线升压电路电连接，用于将由升压器产生的栅极电压钳位在预定电压电平。可以根据可调节钳位电路制造过程中经历的过程变化，利用与可调节钳位电路电连接的微调电路来调整预定电压电平。

8. 发明授权

US6088287A Flash memory architecture employing three layer metal interconnect for word line decoding 有权
标题翻译：闪存架构采用三层金属互连进行字线解码
公开(公告)号：US6088287A
公开(公告)日：2000-07-11
申请号：US379479
申请日：1999-08-23
申请人： Colin S. Bill , Jonathan Shi-Chang Su , Ravi P. Gutala
发明人： Colin S. Bill , Jonathan Shi-Chang Su , Ravi P. Gutala
IPC分类号： G11C16/06 , G11C8/10 , G11C8/12 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/12 , G11C8/10
摘要： The present invention discloses a memory wordline decoder that includes a plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.
摘要翻译：本发明公开了一种存储器字线解码器，其包括与全局x-解码器电连接的多个预解码地址线。子x解码器与全局x解码器电连接，用于从全局x解码器接收电控信号。存储器扇区与子x-解码器电连接。全局x解码器选择性地控制子x解码器以选择存储器扇区中的多个字线。垂直x解码器与全局x解码器和子x解码器电连接。垂直x解码器用于在操作期间由全局x解码器选择预定字线。

9. 发明授权

US5712815A Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells 失效
标题翻译：多位每单元闪存EEPROM能够同时编程和验证存储单元和参考单元
公开(公告)号：US5712815A
公开(公告)日：1998-01-27
申请号：US635995
申请日：1996-04-22
申请人： Colin S. Bill , Sameer S. Haddad
发明人： Colin S. Bill , Sameer S. Haddad
IPC分类号： G11C11/56 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624 , G11C2211/5642 , G11C2211/5645 , G11C2216/14
摘要： An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selected together with a selected memory core cell. A precharge circuit (36a) is used to precharge all of the array bit lines and the reference bit lines to a predetermined potential prior to a program operation. A reference generator circuit (134) is used for selectively generating one of a plurality of target memory core cell bit line program-verify voltages, each one corresponding to one of a plurality of programmable memory states. A switching circuit (P1,N1) is used to selectively connect a program current source to the selected certain ones of the columns of array bit lines containing the selected memory core cells which are to be programmed. A sensing logic circuit (26,27) continuously compares a potential on one of the selected bit lines and one of the plurality of target program-verify voltages. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the selected one of the plurality of target program-verify voltages. The switching circuit is responsive to the low logic level for disconnecting the program current source so as to inhibit further programming of the selected memory core cells.
摘要翻译：提供了一种改进的编程结构，用于执行多个比特单元闪存EEPROM存储单元阵列中的程序操作。存储器核心阵列（12）包括多个存储器单元和具有多个参考核心单元的参考单元阵列（22），所述参考单元阵列与选定的存储器核心单元一起选择。预充电电路（36a）用于在编程操作之前将所有阵列位线和参考位线预充电至预定电位。参考发生器电路（134）用于选择性地产生多个目标存储器核心单元位线程序验证电压中的一个，每一个对应于多个可编程存储器状态之一。切换电路（P1，N1）用于选择性地将程序电流源连接到包含要编程的所选择的存储器核心单元的阵列位线列中选定的某些列。感测逻辑电路（26,27）连续地比较所选位线之一上的电位和多个目标程序验证电压中的一个。感测逻辑电路产生逻辑信号，当所选位线上的电位低于多个目标程序验证电压中选定的一个时，逻辑信号被切换到低逻辑电平。开关电路响应于低逻辑电平以断开程序电流源，从而禁止进一步编程所选择的存储器核心单元。

10. 发明授权

US07355886B1 Method of programming, erasing and reading memory cells in a resistive memory array 有权
标题翻译：在电阻式存储器阵列中编程，擦除和读取存储单元的方法
公开(公告)号：US07355886B1
公开(公告)日：2008-04-08
申请号：US11633791
申请日：2006-12-05
申请人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
发明人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.
摘要翻译：本方法是将数据写入（其可以是编程或擦除）数据到存储器阵列的选定存储单元的方法。阵列包括多个字线，多个位线，多个存储单元，每个存储单元包括串联连接字线和位线的二极管和电阻存储器件，以及多个晶体管，每个晶体管具有第一和第二源极/漏极端子和栅极，每个晶体管具有连接到位线的第一源极/漏极端子。在本方法中，对所选择的字线施加电压，并且将电压施加到其第一源极/漏极端子连接到选定位线的晶体管的第二源极/漏极端子。施加到所选字线的电压大于施加到该晶体管的第二源极/漏极端子的电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式