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1. 发明授权

US07355886B1 Method of programming, erasing and reading memory cells in a resistive memory array 有权
标题翻译：在电阻式存储器阵列中编程，擦除和读取存储单元的方法
公开(公告)号：US07355886B1
公开(公告)日：2008-04-08
申请号：US11633791
申请日：2006-12-05
申请人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
发明人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.
摘要翻译：本方法是将数据写入（其可以是编程或擦除）数据到存储器阵列的选定存储单元的方法。阵列包括多个字线，多个位线，多个存储单元，每个存储单元包括串联连接字线和位线的二极管和电阻存储器件，以及多个晶体管，每个晶体管具有第一和第二源极/漏极端子和栅极，每个晶体管具有连接到位线的第一源极/漏极端子。在本方法中，对所选择的字线施加电压，并且将电压施加到其第一源极/漏极端子连接到选定位线的晶体管的第二源极/漏极端子。施加到所选字线的电压大于施加到该晶体管的第二源极/漏极端子的电压。

2. 发明授权

US07474579B2 Use of periodic refresh in medium retention memory arrays 有权
标题翻译：在介质保留存储器阵列中使用定期更新
公开(公告)号：US07474579B2
公开(公告)日：2009-01-06
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

3. 发明授权

US07450416B1 Utilization of memory-diode which may have each of a plurality of different memory states 有权
标题翻译：利用可能具有多个不同存储器状态中的每一个的存储器二极管
公开(公告)号：US07450416B1
公开(公告)日：2008-11-11
申请号：US11021944
申请日：2004-12-23
申请人： Swaroop Kaza , Juri Krieger , David Gaun , Stuart Spitzer , Richard Kingsborough , Zhida Lan , Colin S. Bill , Wei Daisy Cai , Igor Sokolik
发明人： Swaroop Kaza , Juri Krieger , David Gaun , Stuart Spitzer , Richard Kingsborough , Zhida Lan , Colin S. Bill , Wei Daisy Cai , Igor Sokolik
IPC分类号： G11C11/34
CPC分类号： G11C11/36 , G11C11/56 , G11C13/02 , G11C2213/56 , G11C2213/72
摘要： The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.
摘要翻译：本发明是一种在存储器二极管上进行程序的方法，其中提供可编程以便具有多个不同阈值电压中的每一个的存储器二极管。存储二极管的状态的读取指示存储二极管的阈值电压是如此确定的。

4. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

5. 发明授权

US07894243B2 Methods of programming and erasing resistive memory devices 有权
标题翻译：编程和擦除电阻式存储器件的方法
公开(公告)号：US07894243B2
公开(公告)日：2011-02-22
申请号：US11633800
申请日：2006-12-05
申请人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
发明人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32
摘要： In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.
摘要翻译：在将数据写入电阻存储器件（即编程或擦除）的第一种方法中，连续电势被施加在电阻性存储器件上，其中连续的电势具有增加的持续时间。在将数据写入电阻式存储器件（即编程或擦除）的另一种方法中，在电阻性存储器件上施加电势，并且在施加电位时感测通过存储器件的电流。电位的施加基于通过电阻式存储器件的选定电流水平而结束。

6. 发明申请

US20080130381A1 Methods of programming and erasing resistive memory devices 有权
标题翻译：编程和擦除电阻式存储器件的方法
公开(公告)号：US20080130381A1
公开(公告)日：2008-06-05
申请号：US11633800
申请日：2006-12-05
申请人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
发明人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32
摘要： In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.
摘要翻译：在将数据写入电阻存储器件（即编程或擦除）的第一种方法中，连续电势被施加在电阻性存储器件上，其中连续的电势具有增加的持续时间。在将数据写入电阻式存储器件（即编程或擦除）的另一种方法中，在电阻性存储器件上施加电势，并且在施加电位时感测通过存储器件的电流。电位的施加基于通过电阻式存储器件的选定电流水平而结束。

7. 发明授权

US07035141B1 Diode array architecture for addressing nanoscale resistive memory arrays 有权
标题翻译：用于寻址纳米尺度电阻式存储器阵列的二极管阵列架构
公开(公告)号：US07035141B1
公开(公告)日：2006-04-25
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36 , G11C27/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压。

8. 发明授权

US07259983B2 Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices 有权
标题翻译：用于编程，擦除和读取纳米尺度电阻式存储器件的页缓冲器架构
公开(公告)号：US07259983B2
公开(公告)日：2007-08-21
申请号：US11139227
申请日：2005-05-27
申请人： Colin S. Bill , Wei Daisy Cai
发明人： Colin S. Bill , Wei Daisy Cai
IPC分类号： G11C11/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2013/0085 , G11C2207/2245
摘要： In the present method of programming and erasing the resistive memory devices of a memory device array, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices whose state is to be changed from the previous state.
摘要翻译：在存储器件阵列的电阻性存储器件编程和擦除的现有方法中，在单个命令上，在编程和擦除功能中都提供高电流，以仅对那些状态将被改变的存储器件进行编程和擦除以前的状态。

9. 发明授权

US07145824B2 Temperature compensation of thin film diode voltage threshold in memory sensing circuit 有权
标题翻译：存储器感应电路中薄膜二极管电压阈值的温度补偿
公开(公告)号：US07145824B2
公开(公告)日：2006-12-05
申请号：US11086884
申请日：2005-03-22
申请人： Colin S. Bill , Wei Daisy Cai
发明人： Colin S. Bill , Wei Daisy Cai
IPC分类号： G11C7/04
CPC分类号： G11C13/0016 , B82Y10/00 , G11C7/04 , G11C11/5664 , G11C13/00 , G11C13/0014 , G11C2213/72 , Y10S977/943
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.
摘要翻译：提供了用于存储器感测电路中的薄膜二极管电压电平的温度补偿的系统和方法。本发明包括温度敏感偏置电路和具有温度可变选择装置的阵列芯。阵列芯可以由与纳米级电阻式存储单元串联的薄膜二极管组成。温度敏感偏置电路可以包括与两个电阻器串联的薄膜二极管，并且向阵列芯提供温度补偿偏置电压。温度敏感偏置电路的薄膜二极管跟踪阵列芯的二极管，而两个电阻产生电阻比，以模拟阵列芯上的温度和/或工艺变化的影响。补偿偏置参考电压由温度敏感偏置电路产生，由差分放大器复制，并用于在纳米级电阻存储单元上维持恒定的工作电压电平。

10. 发明授权

US07626882B2 Flash memory device with external high voltage supply 有权
标题翻译：具有外部高压电源的闪存设备
公开(公告)号：US07626882B2
公开(公告)日：2009-12-01
申请号：US11613383
申请日：2006-12-20
申请人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
发明人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
IPC分类号： G11C5/14
CPC分类号： G11C16/12
摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).
摘要翻译：提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合，高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。响应于高电压信号确定时间延迟间隔（412）。

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