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1. 发明授权

US6088287A Flash memory architecture employing three layer metal interconnect for word line decoding 有权
标题翻译：闪存架构采用三层金属互连进行字线解码
公开(公告)号：US6088287A
公开(公告)日：2000-07-11
申请号：US379479
申请日：1999-08-23
申请人： Colin S. Bill , Jonathan Shi-Chang Su , Ravi P. Gutala
发明人： Colin S. Bill , Jonathan Shi-Chang Su , Ravi P. Gutala
IPC分类号： G11C16/06 , G11C8/10 , G11C8/12 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/12 , G11C8/10
摘要： The present invention discloses a memory wordline decoder that includes a plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.
摘要翻译：本发明公开了一种存储器字线解码器，其包括与全局x-解码器电连接的多个预解码地址线。子x解码器与全局x解码器电连接，用于从全局x解码器接收电控信号。存储器扇区与子x-解码器电连接。全局x解码器选择性地控制子x解码器以选择存储器扇区中的多个字线。垂直x解码器与全局x解码器和子x解码器电连接。垂直x解码器用于在操作期间由全局x解码器选择预定字线。

2. 发明授权

US06359824B1 Activation of wordline decoders to transfer a high voltage supply 有权
标题翻译：激活字线解码器传输高压电源
公开(公告)号：US06359824B1
公开(公告)日：2002-03-19
申请号：US09592474
申请日：2000-06-09
申请人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
发明人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/08
摘要： The present invention discloses a method and system for activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in a memory device. A plurality of wordline voltage supply circuits supply voltage for the wordlines. During operation, when the memory device is placed in a test mode requiring application of the predetermined high voltage to the wordlines, the wordline decoder circuits are activated. In addition, a first predetermined voltage that is approximately zero volts is supplied by the wordline voltage supply circuits to the wordline decoder circuits for a first predetermined amount of time. Once the wordline decoder circuits decode the respective wordlines, the first predetermined voltage is transferred to the respective wordlines. The wordline voltage supply circuits then supply a second predetermined voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a second predetermined amount of time. Finally, the wordline voltage supply circuits supply a predetermined high voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a third predetermined amount of time.
摘要翻译：本发明公开了一种用于激活多个字线解码器电路以在存储器件中的测试模式期间将预定高电压传送到多个字线的方法和系统。多个字线电压电路为字线提供电压。在操作期间，当存储器件被放置在需要对字线施加预定高电压的测试模式时，字线解码器电路被激活。此外，大约零伏特的第一预定电压由字线电压供应电路在第一预定时间量内被提供给字线解码器电路。一旦字线解码器电路解码相应的字线，则第一预定电压被传送到相应的字线。然后，字线电压供应电路提供第二预定电压，该第二预定电压由静止激活的字线解码器电路传送到相应的字线第二预定时间量。最后，字线电压供给电路通过静止激活的字线解码器电路提供预定的高电压，该预定的高电压被传送到相应的字线第三预定的时间量。

3. 发明授权

US6046932A Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM 有权
标题翻译：电路实现在闪存EEPROM中编程和过擦除校正模式中的位线漏电流
公开(公告)号：US6046932A
公开(公告)日：2000-04-04
申请号：US417273
申请日：1999-10-13
申请人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
发明人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
IPC分类号： G11C16/06 , G11C16/02 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C16/12 , G11C16/16
CPC分类号： G11C16/3409 , G11C16/30 , G11C16/3404
摘要： A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.
摘要翻译：一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。闪存单元被组织成具有每个块具有列和行的I / O块的阵列。公共阵列源连接和地之间连接一组电阻。电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

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