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1. 发明授权

US5734181A Semiconductor device and manufacturing method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5734181A
公开(公告)日：1998-03-31
申请号：US716713
申请日：1996-09-12
申请人： Ryuji Ohba , Tomohisa Mizuno , Makoto Yoshimi , Kazuya Ohuchi
发明人： Ryuji Ohba , Tomohisa Mizuno , Makoto Yoshimi , Kazuya Ohuchi
IPC分类号： H01L29/165 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/08 , H01L29/78 , H01L29/786 , H01L31/0312 , H01L29/06 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/8234 , H01L21/823814 , H01L27/0605 , H01L29/0847 , H01L29/66575 , H01L29/66659 , H01L29/66772 , H01L29/7838 , H01L29/78618 , H01L21/26586
摘要： A semiconductor device having a MISFET includes: a silicon substrate (2) having a semiconductor region on a surface thereof; a source region (10a) and a drain region (10b) formed in the semiconductor region separately; a channel region formed in the semiconductor region and between the source region and the drain region; a gate electrode (6) formed on the channel region; and a region (8a) formed of Si.sub.1-x C.sub.x overlapping the source region and having a carbon concentration enough to increase an energy gap therein beyond that in the channel region. Further, the MISFET is constructed in such a way that a hetero-junction surface formed between the region formed of Si.sub.1-x C.sub.x (8a) and the other portion of the semiconductor region on the side of the channel region exists at an interface between the source region (10a) and the channel region or in the vicinity thereof, in order to realize a high speed operation, even if the device is microminiaturized.
摘要翻译：具有MISFET的半导体器件包括：在其表面上具有半导体区域的硅衬底（2）; 分别形成在半导体区域中的源极区域（10a）和漏极区域（10b）; 形成在所述半导体区域中，并且在所述源极区域和所述漏极区域之间的沟道区域; 形成在所述沟道区上的栅电极（6）和由Si1-xCx形成的区域（8a），其与源极区域重叠并且具有足以增加其中的能隙的碳浓度超过沟道区域中的能隙。此外，MISFET被构造成使得形成在由Si1-xCx（8a）形成的区域和沟道区域侧的半导体区域的另一部分之间的异质结表面存在于源极区域（10a）和通道区域或其附近，以便实现高速操作，即使该装置被微型化。

2. 发明授权

US5844278A Semiconductor device having a projecting element region 失效
标题翻译：具有突出元件区域的半导体器件
公开(公告)号：US5844278A
公开(公告)日：1998-12-01
申请号：US527636
申请日：1995-09-13
申请人： Tomohisa Mizuno , Yukihiro Ushiku , Makoto Yoshimi , Mamoru Terauchi , Shigeru Kawanaka
发明人： Tomohisa Mizuno , Yukihiro Ushiku , Makoto Yoshimi , Mamoru Terauchi , Shigeru Kawanaka
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66575 , H01L29/1083 , H01L29/41725 , H01L29/4983 , H01L29/66795 , H01L29/7851
摘要： The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.
摘要翻译：本发明提供一种半导体器件，其包括具有突起状半导体元件区域的基板，通过在元件区域的上表面和侧面上的栅极绝缘膜形成的栅电极，以及第一导电型源极区域和漏极该区域以跨越该栅电极的该元件区域的上表面上形成沟道区域的方式设置，并且具有含有比沟道区域表面上的浓度高的第二导电型杂质的高浓度杂质区域在突起状半导体元件区域的中央部。

3. 发明授权

US07009200B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07009200B2
公开(公告)日：2006-03-07
申请号：US10609650
申请日：2003-07-01
申请人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
发明人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
IPC分类号： H01L29/06
CPC分类号： H01L21/2807 , H01L29/1054 , H01L29/4236 , H01L29/665 , H01L29/66613 , H01L29/7834
摘要： A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
摘要翻译：场效应晶体管包括源极和漏极，以及Si 1-xy Ge x C y晶体（1 x）的沟道层 > 0，1> y> = 0）。 Ge组分在沟道层的源极端附近向漏极端增加。

4. 发明授权

US06917096B2 Semiconductor device and method of manufacturing substrate 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06917096B2
公开(公告)日：2005-07-12
申请号：US10611157
申请日：2003-07-02
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/84 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/786 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

5. 发明授权

US06607948B1 Method of manufacturing a substrate using an SiGe layer 有权
标题翻译：使用SiGe层制造衬底的方法
公开(公告)号：US06607948B1
公开(公告)日：2003-08-19
申请号：US09935685
申请日：2001-08-24
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L2184
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

6. 发明申请

US20120168818A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件结构和半导体器件的方法
公开(公告)号：US20120168818A1
公开(公告)日：2012-07-05
申请号：US13412296
申请日：2012-03-05
申请人： Tomohisa Mizuno
发明人： Tomohisa Mizuno
IPC分类号： H01L29/165 , H01L21/336
CPC分类号： H01L29/78654 , H01L29/66742 , H01L29/7848 , H01L29/78618 , H01L29/78684
摘要： Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).
摘要翻译：公开了一种提高半导体元件的性能的方法和具有改进的性能的半导体元件。形成半导体元件结构的方法包括异质结形成步骤，其中在其中保持应变状态的应变半导体层（21）和松弛半导体层（23,25）之间形成异质结。通过从衬底（50）的表面进行离子注入而形成异质结，衬底（50）具有在绝缘氧化膜（40）上部分被覆盖层（30）覆盖的应变半导体层（20），并且改变应变半导体层（20），其中通过缓和应变半导体层（20）的应变状态，在保持应变半导体层（21）的应变状态的同时，不会从覆盖层（30）向松弛的半导体层（23,25）），其中存在与覆盖层（30）的屏蔽。

7. 发明授权

US07659537B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07659537B2
公开(公告)日：2010-02-09
申请号：US11336817
申请日：2006-01-23
申请人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
发明人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L29/1054 , H01L29/4236 , H01L29/665 , H01L29/66613 , H01L29/7834
摘要： A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
摘要翻译：场效应晶体管包括源极和漏极，以及Si1-x-yGexCy晶体（1> x> 0,1> y> = 0）的沟道层。 Ge组分在沟道层的源极端附近向漏极端增加。

8. 发明申请

US20050194585A1 Field effect transistor and a method for manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050194585A1
公开(公告)日：2005-09-08
申请号：US11069980
申请日：2005-03-03
申请人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
发明人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
IPC分类号： H01L27/08 , H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/786 , H01L31/0336
CPC分类号： H01L29/1054 , H01L21/76281 , H01L21/823807 , H01L27/1203 , H01L29/665 , H01L29/66628 , H01L29/66651 , H01L29/66742 , H01L29/78687
摘要： A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0
摘要翻译：制造在器件隔离区域中的场效应晶体管包括晶格应变松弛的Si 1-x N x Ge x层（0

9. 发明授权

US5430313A Transistor with an offset gate structure 失效
标题翻译：具有偏移栅极结构的晶体管
公开(公告)号：US5430313A
公开(公告)日：1995-07-04
申请号：US220045
申请日：1994-03-30
申请人： Jumpei Kumagai , Tomohisa Mizuno
发明人： Jumpei Kumagai , Tomohisa Mizuno
IPC分类号： H01L21/336 , H01L27/088 , H01L29/423 , H01L29/51 , H01L29/78 , H01L23/00
CPC分类号： H01L27/088 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/6656 , H01L29/66575 , H01L29/78 , H01L29/7838 , H01L2924/0002
摘要： At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.
摘要翻译：在p型硅衬底的表面上形成n型源极/漏极扩散层。在源极/漏极扩散层之间的衬底上形成由氧化硅膜形成的栅极绝缘膜，以与扩散层隔离。在栅极绝缘膜上形成栅电极。侧壁形成在栅极绝缘膜和栅电极的从基板向上延伸的侧面上。在本发明中，侧壁由介电常数高于栅极绝缘膜（例如氮化硅膜）的材料构成。

10. 发明授权

US5302844A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5302844A
公开(公告)日：1994-04-12
申请号：US15676
申请日：1993-02-09
申请人： Tomohisa Mizuno , Shizuo Sawada
发明人： Tomohisa Mizuno , Shizuo Sawada
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/92 , H01L29/94 , H01L27/02 , H01L29/68 , H01L29/78
CPC分类号： H01L27/10808 , H01L28/87 , H01L29/94
摘要： According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.
摘要翻译：根据本发明，在半导体基板上形成下电极，向上方向上形成具有蘑菇形截面的电容器的一个电极。形成绝缘膜至少覆盖下电极。上电极形成为与下电极相对并且至少覆盖绝缘膜。

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