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1. 发明申请

US20070187669A1 Field effect transistor and a method for manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070187669A1
公开(公告)日：2007-08-16
申请号：US11783930
申请日：2007-04-13
申请人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
发明人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
IPC分类号： H01L31/00
CPC分类号： H01L29/1054 , H01L21/76281 , H01L21/823807 , H01L27/1203 , H01L29/665 , H01L29/66628 , H01L29/66651 , H01L29/66742 , H01L29/78687
摘要： A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0
摘要翻译：制造在器件隔离区域中的场效应晶体管包括晶格应变松弛的Si 1-x N x Ge x层（0

2. 发明申请

US20050194585A1 Field effect transistor and a method for manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050194585A1
公开(公告)日：2005-09-08
申请号：US11069980
申请日：2005-03-03
申请人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
发明人： Tsutomu Tezuka , Tomohisa Mizuno , Koji Usuda
IPC分类号： H01L27/08 , H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/786 , H01L31/0336
CPC分类号： H01L29/1054 , H01L21/76281 , H01L21/823807 , H01L27/1203 , H01L29/665 , H01L29/66628 , H01L29/66651 , H01L29/66742 , H01L29/78687
摘要： A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0
摘要翻译：制造在器件隔离区域中的场效应晶体管包括晶格应变松弛的Si 1-x N x Ge x层（0

3. 发明授权

US07009200B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07009200B2
公开(公告)日：2006-03-07
申请号：US10609650
申请日：2003-07-01
申请人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
发明人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
IPC分类号： H01L29/06
CPC分类号： H01L21/2807 , H01L29/1054 , H01L29/4236 , H01L29/665 , H01L29/66613 , H01L29/7834
摘要： A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
摘要翻译：场效应晶体管包括源极和漏极，以及Si 1-xy Ge x C y晶体（1 x）的沟道层 > 0，1> y> = 0）。 Ge组分在沟道层的源极端附近向漏极端增加。

4. 发明授权

US06917096B2 Semiconductor device and method of manufacturing substrate 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06917096B2
公开(公告)日：2005-07-12
申请号：US10611157
申请日：2003-07-02
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/84 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/786 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

5. 发明授权

US06607948B1 Method of manufacturing a substrate using an SiGe layer 有权
标题翻译：使用SiGe层制造衬底的方法
公开(公告)号：US06607948B1
公开(公告)日：2003-08-19
申请号：US09935685
申请日：2001-08-24
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L2184
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

6. 发明授权

US07659537B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07659537B2
公开(公告)日：2010-02-09
申请号：US11336817
申请日：2006-01-23
申请人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
发明人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L29/1054 , H01L29/4236 , H01L29/665 , H01L29/66613 , H01L29/7834
摘要： A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
摘要翻译：场效应晶体管包括源极和漏极，以及Si1-x-yGexCy晶体（1> x> 0,1> y> = 0）的沟道层。 Ge组分在沟道层的源极端附近向漏极端增加。

7. 发明申请

US20060118776A1 Field effect transistor 有权
公开(公告)号：US20060118776A1
公开(公告)日：2006-06-08
申请号：US11336817
申请日：2006-01-23
申请人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
发明人： Tsutomu Tezuka , Shinichi Takagi , Tomohisa Mizuno
IPC分类号： H01L31/109
CPC分类号： H01L21/2807 , H01L29/1054 , H01L29/4236 , H01L29/665 , H01L29/66613 , H01L29/7834
摘要： A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

8. 发明授权

US06774390B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06774390B2
公开(公告)日：2004-08-10
申请号：US10369662
申请日：2003-02-21
申请人： Naoharu Sugiyama , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L2906
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/7378 , H01L29/78687
摘要： A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.
摘要翻译：半导体器件包括绝缘层，形成在绝缘层的选定部分上的半导体板，形成在晶格常数不同于半导体板的半导体板的至少一个主侧面上的半导体层，并且其间具有源极和漏极区域和沟道区域，沟道区域的面积大于与绝缘层接触的半导体板的底表面的面积，以及通过栅绝缘形成在沟道区域上的栅电极层。

9. 发明授权

US06509587B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06509587B2
公开(公告)日：2003-01-21
申请号：US09955144
申请日：2001-09-19
申请人： Naoharu Sugiyama , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L350328
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.
摘要翻译：诸如具有应变Si沟道和异质双极晶体管的场效应晶体管的高速和低功耗晶体管彼此集成。这里使用的是这样的复杂结构，其中具有薄膜SiGe缓冲层和应变Si沟道的MOSFET层叠在绝缘膜上，并且通过外延生长在薄膜SiGe层上形成具有SiGe基层的HBT，形成在SiGe基底层上的Si发射极层彼此结合。在MOSFET的绝缘膜上形成的薄膜SiGe层比HBT的对应物薄。在MOSFET的绝缘膜上形成的薄膜SiGe层的Ge浓度高于HBT的绝缘膜。

10. 发明申请

US20120168818A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件结构和半导体器件的方法
公开(公告)号：US20120168818A1
公开(公告)日：2012-07-05
申请号：US13412296
申请日：2012-03-05
申请人： Tomohisa Mizuno
发明人： Tomohisa Mizuno
IPC分类号： H01L29/165 , H01L21/336
CPC分类号： H01L29/78654 , H01L29/66742 , H01L29/7848 , H01L29/78618 , H01L29/78684
摘要： Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).
摘要翻译：公开了一种提高半导体元件的性能的方法和具有改进的性能的半导体元件。形成半导体元件结构的方法包括异质结形成步骤，其中在其中保持应变状态的应变半导体层（21）和松弛半导体层（23,25）之间形成异质结。通过从衬底（50）的表面进行离子注入而形成异质结，衬底（50）具有在绝缘氧化膜（40）上部分被覆盖层（30）覆盖的应变半导体层（20），并且改变应变半导体层（20），其中通过缓和应变半导体层（20）的应变状态，在保持应变半导体层（21）的应变状态的同时，不会从覆盖层（30）向松弛的半导体层（23,25）），其中存在与覆盖层（30）的屏蔽。

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