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1. 发明授权

US06891232B2 Semiconductor device having an injection substance to knock against oxygen and manufacturing method of the same 失效
标题翻译：具有用于冲击氧的注射物质的半导体装置及其制造方法
公开(公告)号：US06891232B2
公开(公告)日：2005-05-10
申请号：US10354094
申请日：2003-01-30
申请人： Kiyotaka Miyano , Kazuya Ohuchi , Ichiro Mizushima
发明人： Kiyotaka Miyano , Kazuya Ohuchi , Ichiro Mizushima
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336 , H01L29/94 , H01L29/76
CPC分类号： H01L29/66628
摘要： A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.
摘要翻译：半导体器件包括：半导体衬底; 形成在所述半导体衬底的顶表面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 在半导体衬底中形成的扩散层用作源极层和漏极层; 以及形成为覆盖所述扩散层的硅化物层; 其中氧浓度最大的氧浓度峰在垂直于所述顶表面的平面截取的横截面中处于比所述顶表面低的水平。

2. 发明授权

US06878579B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06878579B2
公开(公告)日：2005-04-12
申请号：US10917345
申请日：2004-08-13
申请人： Kazuya Ohuchi , Hironobu Fukui
发明人： Kazuya Ohuchi , Hironobu Fukui
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L29/78 , H01L21/335 , H01L21/425
CPC分类号： H01L29/4983 , H01L21/2807 , H01L21/28105 , H01L21/823437 , H01L21/82345 , H01L21/823468 , H01L29/42376 , H01L29/4238 , H01L29/66666 , H01L29/7827 , Y10S438/904 , Y10S438/917 , Y10S438/933
摘要： An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

3. 发明授权

US06791106B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06791106B2
公开(公告)日：2004-09-14
申请号：US10420884
申请日：2003-04-23
申请人： Kazuya Ohuchi , Hironobu Fukui
发明人： Kazuya Ohuchi , Hironobu Fukui
IPC分类号： H01L2906
CPC分类号： H01L29/4983 , H01L21/2807 , H01L21/28105 , H01L21/823437 , H01L21/82345 , H01L21/823468 , H01L29/42376 , H01L29/4238 , H01L29/66666 , H01L29/7827 , Y10S438/904 , Y10S438/917 , Y10S438/933
摘要： An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
摘要翻译：本发明的一个方面包括第一导电型半导体区域; 形成在所述第一导电型半导体区域上的栅电极; 形成在所述第一导电型半导体区域中的所述栅电极的正下方的沟道区域; 以及构成在第一导电型半导体区域的沟道区的相对侧的源/漏区的第二导电型第一扩散层，栅电极由多晶硅锗形成，其中锗浓度从漏极区域侧到源极区域侧，并且根据栅极电极中的锗浓度，在第一导电型半导体区域中的栅电极正下方的杂质浓度从源极区域侧向漏极区域侧连续增加。

4. 发明授权

US06498374B1 MOS semiconductor device having gate insulating film containing nitrogen 失效
标题翻译：具有含有氮的栅极绝缘膜的MOS半导体器件
公开(公告)号：US06498374B1
公开(公告)日：2002-12-24
申请号：US09609314
申请日：2000-06-30
申请人： Kazuya Ohuchi
发明人： Kazuya Ohuchi
IPC分类号： H01L2978
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/823462 , H01L29/518
摘要： Disclosed is a MOS semiconductor device, which comprises a semiconductor substrate; a gate insulating film formed on the semiconductor substrate, the gate insulating film containing nitrogen; a gate electrode selectively formed on the gate insulating film; and an oxide film formed on a surface of the gate electrode and the semiconductor substrate, wherein a thickness of a first portion of the gate insulating film which overlaps vertically the gate electrode is one third or less that of a second portion of the gate insulating film disposed at a corner portion of the gate electrode. According to such constitution of the MOS transistor device of the present invention, by allowing the gate insulating film to contain nitrogen, an increase in a thickness of the gate insulating film toward the semiconductor substrate than required can be suppressed, and hence lowering of a gate voltage can be prevented, resulting in preventing a controllability deterioration of the MOS transistor device.
摘要翻译：公开了一种MOS半导体器件，其包括半导体衬底; 形成在所述半导体基板上的栅极绝缘膜，所述栅极绝缘膜含有氮; 选择性地形成在栅极绝缘膜上的栅电极; 以及形成在所述栅极电极和所述半导体基板的表面上的氧化膜，其中，所述栅极绝缘膜的与所述栅电极垂直重叠的第一部分的厚度为所述栅极绝缘膜的第二部分的厚度的三分之一以下设置在栅电极的角部。根据本发明的MOS晶体管器件的结构，通过允许栅极绝缘膜含有氮，栅极绝缘膜的厚度朝向半导体衬底的增加比所需要的可以抑制栅极电压的降低，从而防止MOS晶体管器件的可控性劣化。

5. 发明授权

US5734181A Semiconductor device and manufacturing method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5734181A
公开(公告)日：1998-03-31
申请号：US716713
申请日：1996-09-12
申请人： Ryuji Ohba , Tomohisa Mizuno , Makoto Yoshimi , Kazuya Ohuchi
发明人： Ryuji Ohba , Tomohisa Mizuno , Makoto Yoshimi , Kazuya Ohuchi
IPC分类号： H01L29/165 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/08 , H01L29/78 , H01L29/786 , H01L31/0312 , H01L29/06 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/8234 , H01L21/823814 , H01L27/0605 , H01L29/0847 , H01L29/66575 , H01L29/66659 , H01L29/66772 , H01L29/7838 , H01L29/78618 , H01L21/26586
摘要： A semiconductor device having a MISFET includes: a silicon substrate (2) having a semiconductor region on a surface thereof; a source region (10a) and a drain region (10b) formed in the semiconductor region separately; a channel region formed in the semiconductor region and between the source region and the drain region; a gate electrode (6) formed on the channel region; and a region (8a) formed of Si.sub.1-x C.sub.x overlapping the source region and having a carbon concentration enough to increase an energy gap therein beyond that in the channel region. Further, the MISFET is constructed in such a way that a hetero-junction surface formed between the region formed of Si.sub.1-x C.sub.x (8a) and the other portion of the semiconductor region on the side of the channel region exists at an interface between the source region (10a) and the channel region or in the vicinity thereof, in order to realize a high speed operation, even if the device is microminiaturized.
摘要翻译：具有MISFET的半导体器件包括：在其表面上具有半导体区域的硅衬底（2）; 分别形成在半导体区域中的源极区域（10a）和漏极区域（10b）; 形成在所述半导体区域中，并且在所述源极区域和所述漏极区域之间的沟道区域; 形成在所述沟道区上的栅电极（6）和由Si1-xCx形成的区域（8a），其与源极区域重叠并且具有足以增加其中的能隙的碳浓度超过沟道区域中的能隙。此外，MISFET被构造成使得形成在由Si1-xCx（8a）形成的区域和沟道区域侧的半导体区域的另一部分之间的异质结表面存在于源极区域（10a）和通道区域或其附近，以便实现高速操作，即使该装置被微型化。

6. 发明授权

US07456096B2 Method of manufacturing silicide layer for semiconductor device 失效
标题翻译：制造半导体器件硅化物层的方法
公开(公告)号：US07456096B2
公开(公告)日：2008-11-25
申请号：US11530724
申请日：2006-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L29/45
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译：可以降低硅化镍膜与硅之间界面处的界面电阻。半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。

7. 发明申请

US20080088021A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20080088021A1
公开(公告)日：2008-04-17
申请号：US11868011
申请日：2007-10-05
申请人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
发明人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
IPC分类号： H01L23/532 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76831 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
摘要翻译：在本发明的一个方面中，半导体器件可以包括半导体衬底，设置在半导体衬底上的硅化物层，设置在半导体衬底上的电介质层，设置在硅化物层上的接触层，设置在该半导体衬底上的金属层电介质层，经由接触层与硅化物层电连接，设置在介电层和金属层之间的扩散阻挡层，其中接触层包括设置在金属层中的第一金属元件，设置在金属层中的第二金属元件扩散阻挡层和设置在硅化物层和Si元件中的第三金属中的至少一个。

8. 发明授权

US07148096B2 Method of manufacturing a semiconductor device having a gate electrode containing polycrystalline silicon-germanium 失效
标题翻译：制造具有含有多晶硅锗的栅极的半导体器件的方法
公开(公告)号：US07148096B2
公开(公告)日：2006-12-12
申请号：US10853209
申请日：2004-05-26
申请人： Kazuya Ohuchi
发明人： Kazuya Ohuchi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/4983 , H01L21/2807 , H01L21/28105 , H01L21/823437 , H01L21/82345 , H01L21/823468 , H01L29/42376 , H01L29/4238 , H01L29/66666 , H01L29/7827 , Y10S438/933
摘要： An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor region, a channel region formed immediately below the gate electrode in the first conductive type semiconductor region, and a second conductive type first diffusion layers constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which the germanium concentration of at least one of the source side and the drain side is higher than that of the central portion.
摘要翻译：本发明的一个方面包括形成在半导体衬底中的第一导电类型半导体区域，形成在第一导电型半导体区域上的栅极电极，形成在第一导电类型半导体区域中的栅电极正下方的沟道区域，以及第二导电型第一扩散层，其构成在第一导电类型半导体区域中的沟道区的相对侧的源/漏区，栅电极由多晶硅锗形成，其中源的至少一个的锗浓度侧和漏侧比中心部高。

9. 发明授权

US06897534B2 Semiconductor device having gate electrode of stacked structure including polysilicon layer and metal layer and method of manufacturing the same 失效
标题翻译：具有包括多晶硅层和金属层的堆叠结构的栅电极的半导体器件及其制造方法
公开(公告)号：US06897534B2
公开(公告)日：2005-05-24
申请号：US10654925
申请日：2003-09-05
申请人： Kazuya Ohuchi , Atsushi Azuma
发明人： Kazuya Ohuchi , Atsushi Azuma
IPC分类号： H01L29/78 , H01L21/28 , H01L21/318 , H01L21/336 , H01L21/60 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/76897 , H01L21/28061 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.
摘要翻译：本发明提供了一种半导体器件，包括由多晶硅层和金属层组成的堆叠结构的栅极电极，形成在栅电极上的帽绝缘膜和形成在栅极侧壁上的栅极侧壁膜电极。盖绝缘膜由含有氧化硅基层和氮化硅层的绝缘膜构成，用于保护栅电极的上表面。此外，栅极侧壁膜由含有氮化硅膜和氧化硅膜的绝缘膜构成，用于保护栅电极的侧面。

10. 发明申请

US20130049199A1 SILICIDATION OF DEVICE CONTACTS USING PRE-AMORPHIZATION IMPLANT OF SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：使用半导体基板的预加工植入物进行器件接触的硅化
公开(公告)号：US20130049199A1
公开(公告)日：2013-02-28
申请号：US13222469
申请日：2011-08-31
申请人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
发明人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
IPC分类号： H01L23/532 , H01L21/336 , H01L21/768
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/00 , H01L29/665 , H01L29/7833
摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.
摘要翻译：具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

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