专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060119415A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060119415A1
公开(公告)日：2006-06-08
申请号：US11293378
申请日：2005-12-05
申请人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
发明人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
IPC分类号： H01H37/76
CPC分类号： H01L23/5258 , G11C17/16 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
摘要翻译：一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

2. 发明授权

US07218560B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07218560B2
公开(公告)日：2007-05-15
申请号：US11293378
申请日：2005-12-05
申请人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
发明人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
IPC分类号： G11C7/00
CPC分类号： H01L23/5258 , G11C17/16 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
摘要翻译：一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

3. 发明授权

US07888769B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07888769B2
公开(公告)日：2011-02-15
申请号：US11756196
申请日：2007-05-31
申请人： Masaki Kondo , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
发明人： Masaki Kondo , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
IPC分类号： H01L29/00
CPC分类号： H01L27/0251 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.
摘要翻译：根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

4. 发明申请

US20080079473A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080079473A1
公开(公告)日：2008-04-03
申请号：US11864041
申请日：2007-09-28
申请人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
发明人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
IPC分类号： H03K3/356
CPC分类号： H03K3/356191 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.
摘要翻译：第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

5. 发明授权

US08027216B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08027216B2
公开(公告)日：2011-09-27
申请号：US12550663
申请日：2009-08-31
申请人： Ryo Fukuda , Yohji Watanabe
发明人： Ryo Fukuda , Yohji Watanabe
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/04 , G11C11/406 , G11C11/40615 , G11C2211/4016 , G11C2211/4067
摘要： A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.
摘要翻译：存储器可以包括：字线; 位线存储器阵列块，包括存储器单元，每个存储器阵列块是数据读取操作或数据写入操作的单元; 行解码器，被配置为选择性地驱动所述字线; 配置成检测数据的感测放大器; 以及为每个存储器单元块提供的访问计数器，所述访问计数器对访问所述存储器阵列块的次数进行计数，以便读取数据或写入数据，以及当所述访问次数达到预定的次数时激活刷新请求信号次数，其中在访问计数器的刷新请求信号的激活周期期间，行解码器周期性地并且顺序地激活对应于访问计数器的存储器阵列块的字线，并且读出放大器执行刷新操作存储单元连接到激活的字线。

6. 发明授权

US07732840B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07732840B2
公开(公告)日：2010-06-08
申请号：US11864041
申请日：2007-09-28
申请人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
发明人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
IPC分类号： H01L21/76
CPC分类号： H03K3/356191 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.
摘要翻译：第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

7. 发明申请

US20070278580A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20070278580A1
公开(公告)日：2007-12-06
申请号：US11756196
申请日：2007-05-31
申请人： Masaki KONDO , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
发明人： Masaki KONDO , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
IPC分类号： H01L23/62 , H02H3/20
CPC分类号： H01L27/0251 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.
摘要翻译：根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

8. 发明申请

US20120068256A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120068256A1
公开(公告)日：2012-03-22
申请号：US13232492
申请日：2011-09-14
申请人： Ryo Fukuda , Yoshihisa Iwata
发明人： Ryo Fukuda , Yoshihisa Iwata
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0416 , H01L27/11565 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.
摘要翻译：在半导体衬底上方形成绝缘膜。第一导电层形成在电介质膜中并沿第一方向延伸。第一导电层连接到第一选择晶体管。形成在电介质膜中并沿第一方向延伸的第二导电层。第二导电层连接到第二选择晶体管。半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。在半导体层上形成栅极绝缘膜。栅极绝缘膜包括作为其一部分的电荷累积膜。第三导电层被栅极绝缘膜包围。

9. 发明授权

US07958279B2 Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission 失效
标题翻译：用于在一个发射机和多个移位寄存器之间传送数据的异步串行数据装置，避免传输期间的偏斜
公开(公告)号：US07958279B2
公开(公告)日：2011-06-07
申请号：US12405953
申请日：2009-03-17
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F13/00 , G06F13/12
CPC分类号： G06F13/4282
摘要： A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.
摘要翻译：一种半导体集成电路装置，包括数据发送器电路和多个数据接收器电路，每个数据接收器电路具有数据转换器电路，其恢复识别号码数据的每一位并将数据从数据发送器电路的移位寄存器传送到2位通过第一和第二传输线传输的补充数据;接收控制电路，当经由第三传输线接收到传送完成信号时，将分配的识别号与恢复的标识号数据进行比较，以及移位寄存器接收控制电路，其中每个接收控制电路根据识别号码数据和所分配的识别号码之间的比较结果，将对应于识别号码数据的数据发送器电路发送的传送数据提供给相关联的移位寄存器。

10. 发明授权

US07609551B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式