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1. 发明授权

US07888769B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07888769B2
公开(公告)日：2011-02-15
申请号：US11756196
申请日：2007-05-31
申请人： Masaki Kondo , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
发明人： Masaki Kondo , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
IPC分类号： H01L29/00
CPC分类号： H01L27/0251 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.
摘要翻译：根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

2. 发明申请

US20060119415A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060119415A1
公开(公告)日：2006-06-08
申请号：US11293378
申请日：2005-12-05
申请人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
发明人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
IPC分类号： H01H37/76
CPC分类号： H01L23/5258 , G11C17/16 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
摘要翻译：一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

3. 发明申请

US20050122802A1 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US20050122802A1
公开(公告)日：2005-06-09
申请号：US11040851
申请日：2005-01-20
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C8/02 , G11C29/00 , G11C29/26 , G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.
摘要翻译：提供了一种半导体存储装置，其中只有一个缺陷元件被行冗余元件代替，以便在存储单元阵列中的多个元件是多个元件中的多个元件中的至少一个元件是有缺陷的情况下补偿缺陷同时激活。半导体存储装置包括阵列控制电路，其被配置为通过基于信号来防止接收到字线状态信号来中断故障元件的操作，以确定是否执行行冗余替换处理。字线状态信号通过单个信号线输入到单元阵列单元中的多个存储块。

4. 发明授权

US06856561B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06856561B2
公开(公告)日：2005-02-15
申请号：US10657790
申请日：2003-09-08
申请人： Daisuke Kato , Munehiro Yoshida , Yohji Watanabe
发明人： Daisuke Kato , Munehiro Yoshida , Yohji Watanabe
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808 , G11C29/785
摘要： A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.
摘要翻译：半导体存储器件具有单元阵列，每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元，每个在单元阵列内被定义为一组存储单元，每个存储单元被布置在所述单元阵列的第二方向上，每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元，用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件用于替换电池阵列内的有缺陷的第二正常元件的元件。在单元阵列第一/第二修复区域内被定义为具有允许由每个第一/第二冗余元件替换的第一/第二正常元素的组。

5. 发明授权

US06741509B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US06741509B2
公开(公告)日：2004-05-25
申请号：US10053524
申请日：2002-01-16
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.
摘要翻译：提供了一种半导体存储装置，其中只有一个缺陷元件被行冗余元件代替，以便在存储单元阵列中的多个元件是多个元件中的多个元件中的至少一个元件是有缺陷的情况下补偿缺陷同时激活。半导体存储装置包括阵列控制电路，其被配置为通过基于信号来防止接收到字线状态信号来中断故障元件的操作，以确定是否执行行冗余替换处理。字线状态信号通过单个信号线输入到单元阵列单元中的多个存储块。

6. 发明授权

US6055197A Semiconductor memory device with simultaneously activated elements and a redundancy scheme thereof 失效
标题翻译：具有同时激活元件的半导体存储器件及其冗余方案
公开(公告)号：US6055197A
公开(公告)日：2000-04-25
申请号：US213651
申请日：1998-12-16
申请人： Daisuke Kato , Yohji Watanabe
发明人： Daisuke Kato , Yohji Watanabe
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/808 , G11C29/83
摘要： In a semiconductor memory device, assuming that the ratio of a memory capacity of a region of a memory array per one of elements, which are simultaneously activated in the memory array in which x elements (x is an integer of two or more) are simultaneously activated and which is divided into a plurality of repair regions, each of which has at least two elements, to a memory capacity in one of the repair regions corresponding to one of spare element groups is y (y is an integer of one or more), each of the repair regions is designed so that a plurality of elements are simultaneously activated in its own repair region, and each of the spare element groups is designed so that the number of spare elements simultaneously activated in each of the spare element groups is one. Thus, it is possible to effectively reduce electric current consumption in the total of redundant control circuits.
摘要翻译：在半导体存储器件中，假定存储器阵列中存储器阵列的区域的存储容量与x元素（x为2以上的整数）同时被激活的存储器阵列中的每一个元件的存储容量之比被激活，并且其被分成多个修复区域，每个修复区域具有至少两个元件，其中一个修复区域对应于备用元件组之一的存储器容量是y（y是一个或多个的整数）每个修理区域被设计成使得多个元件在其自己的修复区域中同时被激活，并且每个备用元件组被设计成使得在每个备用元件组中同时激活的备用元件的数量是一个。因此，可以有效地减少总共冗余控制电路中的电流消耗。

7. 发明授权

US5991211A Semiconductor memory device with redundancy control circuits 失效
标题翻译：具有冗余控制电路的半导体存储器件
公开(公告)号：US5991211A
公开(公告)日：1999-11-23
申请号：US181977
申请日：1998-10-29
申请人： Daisuke Kato , Yohji Watanabe
发明人： Daisuke Kato , Yohji Watanabe
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C29/84
摘要： A semiconductor memory device has sets of address fuses which are arranged in a plurality of fuse rows in order to provide a larger number of redundant elements. The sets of address fuses are associated with addresses, respectively, and at least one address fuse included in each of the sets of the address fuses is provided in only one of the fuse rows. Address buses are provided such that the number of address lines associated with the sets of the address fuses is less than the number of fuse rows. One of the address lines is located closer to one of the fuse rows which includes associated address fuses than a center line between the one of the fuse rows and another one of the fuse rows which is adjacent to the one of the fuse rows is. The address lines are connected to redundant element control circuits through local lines.
摘要翻译：半导体存储器件具有布置在多个熔丝行中的地址熔丝组，以便提供更多数量的冗余元件。地址熔丝组分别与地址相关联，并且仅在一个熔丝行中提供包含在每个地址熔丝组中的至少一个地址熔丝。提供地址总线，使得与地址熔丝组相关联的地址线的数量小于熔丝行的数量。一个地址线位于更靠近其中一个保险丝列的位置，该保险丝列包括相关联的地址熔丝，而不是熔丝列之一与另一个与熔丝列之一相邻的熔丝行之一的中心线。地址线通过本地线连接到冗余元件控制电路。

8. 发明授权

US5963489A Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device 失效
标题翻译：用于可修复半导体存储器件中冗余字线替换的方法和装置
公开(公告)号：US5963489A
公开(公告)日：1999-10-05
申请号：US47086
申请日：1998-03-24
申请人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.
摘要翻译：一种用于修复半导体存储器件的方法和装置。提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第正常补码字线。地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

9. 发明授权

US5023476A Semiconductor device with power supply mode-change controller for reliability testing 失效
标题翻译：具有电源模式变换控制器的半导体器件，用于可靠性测试
公开(公告)号：US5023476A
公开(公告)日：1991-06-11
申请号：US299424
申请日：1989-01-23
申请人： Yohji Watanabe , Tohru Furuyama
发明人： Yohji Watanabe , Tohru Furuyama
IPC分类号： H01L21/66 , G05F1/46 , G06F1/04 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04
CPC分类号： G11C5/147 , G05F1/465 , H01L2924/0002
摘要： An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.

10. 发明授权

US4967395A Dram with (1/2)VCC precharge and selectively operable limiting circuit 失效
标题翻译：具有（1/2）VCC预充电和选择性操作的限制电路
公开(公告)号：US4967395A
公开(公告)日：1990-10-30
申请号：US304173
申请日：1989-01-31
申请人： Yohji Watanabe , Tohru Furuyama
发明人： Yohji Watanabe , Tohru Furuyama
IPC分类号： G11C11/409 , G11C11/4074 , G11C11/4076 , G11C11/4094
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4094
摘要： An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.
摘要翻译：幅度限制电路被布置在具有（1/2）VCC预充电的DRAM中，以使得在活动周期中充电和放电的每对位线的预充电电压和“H”电平输出之间的幅度相等，每对位线的预充电电压和“L”电平输出。

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