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1. 发明授权

US07935629B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07935629B2
公开(公告)日：2011-05-03
申请号：US11876230
申请日：2007-10-22
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

2. 发明授权

US07626220B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07626220B2
公开(公告)日：2009-12-01
申请号：US11876379
申请日：2007-10-22
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

3. 发明授权

US07317217B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07317217B2
公开(公告)日：2008-01-08
申请号：US10944626
申请日：2004-09-17
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

4. 发明授权

US07696565B2 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US07696565B2
公开(公告)日：2010-04-13
申请号：US11696331
申请日：2007-04-04
申请人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

5. 发明授权

US07241649B2 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US07241649B2
公开(公告)日：2007-07-10
申请号：US10977768
申请日：2004-10-29
申请人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

6. 发明授权

US07317605B2 Method and apparatus for improving performance margin in logic paths 失效
标题翻译：提高逻辑路径性能余量的方法和装置
公开(公告)号：US07317605B2
公开(公告)日：2008-01-08
申请号：US10798911
申请日：2004-03-11
申请人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H02H5/04
CPC分类号： G11C5/147 , G06F1/206 , G06F1/26 , G11C7/04 , G11C11/4074
摘要： An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.
摘要翻译：公开了一种用于改善半导体芯片上的逻辑路径的时序余量的装置和方法。诸如CMOS（互补金属氧化物半导体）的典型逻辑实施例具有随着电源电压增加而变短的路径延迟。本发明的实施例将产品数据存储在每个特定芯片上。产品数据包括例如但不限于具有用于特定芯片的存储器中的特定芯片的低限电压和上限电压，极限温度和性能的电压范围。每个芯片都有一个电压控制器，一个定时器和一个热量监视器。电压控制器与电压调节器通信，动态地使耦合到芯片的电压在电压范围内尽可能高，受限于极限温度。

7. 发明授权

US07227183B2 Polysilicon conductor width measurement for 3-dimensional FETs 失效
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US07227183B2
公开(公告)日：2007-06-05
申请号：US10944622
申请日：2004-09-17
申请人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L21/66
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

8. 发明授权

US06774734B2 Ring oscillator circuit for EDRAM/DRAM performance monitoring 有权
标题翻译：环形振荡器电路用于EDRAM / DRAM性能监控
公开(公告)号：US06774734B2
公开(公告)日：2004-08-10
申请号：US10306200
申请日：2002-11-27
申请人： Todd Alan Christensen , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H03B100
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C2029/0401 , H03K3/0315
摘要： Circuitry and methods are disclosed for quantitatively characterizing the delay of Embedded Dynamic Random Access Memory (EDRAM) and Dynamic Random Access Memory (DRAM). The performance critical portion of the memory is placed in a ring oscillator designed such that the delay through the portion, from a rising input to the memory to a rising output, can be accurately determined. Recently, such memory elements have begun to be implemented on chips along with high-speed logic circuitry. However, the performance characteristics of the memory elements do not track the performance characteristics of the logic circuitry. The current invention allows the memory performance to be characterized along with, or separately from, characterization of the logic circuitry.
摘要翻译：公开了用于定量表征嵌入式动态随机存取存储器（EDRAM）和动态随机存取存储器（DRAM）的延迟的电路和方法。存储器的性能关键部分放置在环形振荡器中，该环形振荡器被设计成使得可以准确地确定从上升输入到存储器到上升输出的部分的延迟。最近，这种存储元件已经开始在芯片上与高速逻辑电路一起实现。然而，存储器元件的性能特征不跟踪逻辑电路的性能特性。本发明允许存储器性能与逻辑电路的表征一起被描述或者与其分开。

9. 发明授权

US07009905B2 Method and apparatus to reduce bias temperature instability (BTI) effects 失效
标题翻译：降低偏倚温度不稳定性（BTI）效应的方法和装置
公开(公告)号：US07009905B2
公开(公告)日：2006-03-07
申请号：US10744175
申请日：2003-12-23
申请人： Anthony Gus Aipperspach , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Anthony Gus Aipperspach , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/1045
摘要： Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress condition. Many storage elements in an electronic system store the same data for virtually the life of the system, resulting in significant BTI caused VT shifts in FETs in the storage elements. An embodiment of the invention ensures that a particular storage element is in a first state for a first portion of time the electronic system operates, during which data is stored in a storage element in a first phase, and that the particular storage element is in a second state for a second portion of time the electronic system operates, during which data is stored in the storage element in a second phase.
摘要翻译：公开了允许用场效应晶体管（FET）实现的电子系统减少由偏置温度不稳定性（BTI）引起的阈值电压偏移的方法和装置。当FET处于特定的电压应力状态时，BTI引起VT偏移累加。电子系统中的许多存储元件几乎在系统中存储相同的数据，导致显着的BTI导致存储元件中FET的VT位移。本发明的一个实施例确保了特定存储元件在电子系统操作的第一时间段处于第一状态，在此期间数据被存储在第一阶段的存储元件中，并且特定存储元件处于电子系统操作的第二部分时间的第二状态，在此期间数据以第二阶段存储在存储元件中。

10. 发明授权

US06879177B1 Method and testing circuit for tracking transistor stress degradation 失效
标题翻译：跟踪晶体管应力退化的方法和测试电路
公开(公告)号：US06879177B1
公开(公告)日：2005-04-12
申请号：US10731072
申请日：2003-12-09
申请人： Ronald Jay Bolam , William Paul Hovis , Terrance Wayne Kueper
发明人： Ronald Jay Bolam , William Paul Hovis , Terrance Wayne Kueper
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2879 , G01R31/2856 , G01R31/2884
摘要： A method and testing circuit are provided for tracking transistor stress degradation. A first array of P-channel field effect transistors (PFETs) is connected in parallel. The first array of PFETs is stressed by applying a low gate input and a high source and a high drain to the PFETs during a stress period. The first array of PFETs is tested by operating the PFETs in a saturated region during a test period. A reference array of PFETs is not stressed during the stress period. The reference array of PFETs is activated for testing to compare a saturated drain current performance with the first array of PFETs during the test period.
摘要翻译：提供了一种跟踪晶体管应力退化的方法和测试电路。 P沟道场效应晶体管（PFET）的第一阵列并联连接。第一阵列PFET通过在应力周期期间向PFET施加低栅极输入和高源极和高漏极而受到压力。在测试期间，通过在饱和区域中操作PFET来测试第一阵列PFET。在应力周期期间，PFET的参考阵列不受应力。在测试期间，PFET的参考阵列被激活用于测试以将饱和漏极电流性能与第一阵列PFET进行比较。

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