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1. 发明授权

US08574982B2 Implementing eDRAM stacked FET structure 有权
标题翻译：实现eDRAM堆叠FET结构
公开(公告)号：US08574982B2
公开(公告)日：2013-11-05
申请号：US12712521
申请日：2010-02-25
申请人： Karl Robert Erickson , David Paul Paulsen , John Edward Sheets, II , Kelly L. Williams
发明人： Karl Robert Erickson , David Paul Paulsen , John Edward Sheets, II , Kelly L. Williams
IPC分类号： H01L21/8249
CPC分类号： H01L27/10841 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L28/40
摘要： A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.
摘要翻译：一种用于实现嵌入式动态随机存取存储器（eDRAM）的方法和电路，以及设置有该电路所在的设计结构。嵌入式动态随机存取存储器（eDRAM）电路包括堆叠场效应晶体管（FET）和电容器。电容器直接在FET的顶部制造以构建eDRAM。

2. 发明授权

US08535393B2 Method and apparatus for measurement and control of photomask to substrate alignment 失效
公开(公告)号：US08535393B2
公开(公告)日：2013-09-17
申请号：US12983915
申请日：2011-01-04
申请人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
发明人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
IPC分类号： H01L21/027
CPC分类号： G03F7/70891 , G03F7/70875 , G03F9/7076
摘要： A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.

3. 发明授权

US08314001B2 Vertical stacking of field effect transistor structures for logic gates 失效
标题翻译：用于逻辑门的场效应晶体管结构的垂直堆叠
公开(公告)号：US08314001B2
公开(公告)日：2012-11-20
申请号：US12757145
申请日：2010-04-09
申请人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
发明人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/743 , H01L21/84 , H01L27/0688 , H01L27/1203
摘要： Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
摘要翻译：产生垂直堆叠场效应晶体管（FET），其中第一FET和第二FET独立控制。垂直堆叠的FET可以串联或并联连接，从而适合用作NAND电路或NOR电路的一部分。在第一FET的源极和漏极上的外延生长，并且具有与第一FET的源极和漏极类似的掺杂，提供第二FET的源极和漏极。与第一FET的源极和漏极的掺杂相反的类型的另外的外延生长为第二FET提供了一个主体。

4. 发明授权

US07935629B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07935629B2
公开(公告)日：2011-05-03
申请号：US11876230
申请日：2007-10-22
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

5. 发明申请

US20100032799A1 Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips 失效
标题翻译：在集成电路芯片上实现热点热还原实现去耦电容
公开(公告)号：US20100032799A1
公开(公告)日：2010-02-11
申请号：US12186837
申请日：2008-08-06
申请人： Gerald Keith Bartley , Todd Alan Christensen , Paul Eric Dahlen , John Edward Sheets, II
发明人： Gerald Keith Bartley , Todd Alan Christensen , Paul Eric Dahlen , John Edward Sheets, II
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0805
摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.
摘要翻译：提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。背面热连接包括从SOI结构的背面延伸到硅衬底层的后侧蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

6. 发明申请

US20090195787A1 Method and Apparatus for Measurement and Control of Photomask to Substrate Alignment 失效
标题翻译：用于测量和控制光掩模到基板对准的方法和装置
公开(公告)号：US20090195787A1
公开(公告)日：2009-08-06
申请号：US12026763
申请日：2008-02-06
申请人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
发明人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
IPC分类号： G01B11/02
CPC分类号： G03F7/70891 , G03F7/70875 , G03F9/7076
摘要： A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.
摘要翻译：将基板与光掩模对准的方法，结构，系统。该方法包括：将入射光通过透明透明区域的图案，通过透镜通过光掩模的不透明到入射光区域透射到形成在基板上的光电二极管上，电连接发光二极管形成在基板上，发光二极管发射波长不同于入射光波长的光; 测量来自发光二极管的发射光的强度; 以及基于所发射的光的测量强度来调整光掩模与衬底的对准。

7. 发明授权

US06492244B1 Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices 失效
标题翻译：用于实现绝缘体（SOI）器件的埋地双轨配电和集成去耦电容的方法和半导体结构
公开(公告)号：US06492244B1
公开(公告)日：2002-12-10
申请号：US09990478
申请日：2001-11-21
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L2176
CPC分类号： H01L27/1203 , H01L21/76243
摘要： Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.
摘要翻译：提供了用于实现用于绝缘体上硅（SOI）器件的掩埋双轨配电和集成去耦电容的方法和半导体结构。提供了限定一个配电轨的体硅衬底层。执行高能深氧注入以产生深埋氧化层和第一中间硅层。深埋氧化层设置在体硅衬底层和第一中间硅层之间。第一中间硅层限定另一配电轨。执行较低能量的氧注入以产生浅埋氧化物层和第二中间硅层。浅埋氧化层设置在第一中间硅层和第二中间硅层之间。形成与本体硅衬底层的连接，而不与中间硅层电连接。形成与第一中间硅层的连接，而不与第二中间硅层电连接。

8. 发明申请

US20110096310A1 METHOD AND APPARATUS FOR MEASUREMENT AND CONTROL OF PHOTOMASK TO SUBSTRATE ALIGNMENT 失效
标题翻译：用于测量和控制光电子基板对准的方法和装置
公开(公告)号：US20110096310A1
公开(公告)日：2011-04-28
申请号：US12983591
申请日：2011-01-03
申请人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
发明人： Axel Aguado Granados , Benjamin Aaron Fox , Nathaniel James Gibbs , Andrew Benson Maki , John Edward Sheets, II , Trevor Joseph Timpane
IPC分类号： G03B27/52
CPC分类号： G03F7/70891 , G03F7/70875 , G03F9/7076
摘要： A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.
摘要翻译：将基板与光掩模对准的方法，结构，系统。该方法包括：将入射光通过透明透明区域的图案，通过透镜通过光掩模的不透明到入射光区域透射到形成在基板上的光电二极管上，电连接发光二极管形成在基板上，发光二极管发射波长不同于入射光波长的光; 测量来自发光二极管的发射光的强度; 以及基于所发射的光的测量强度来调整光掩模与衬底的对准。

9. 发明申请

US20100140808A1 Power Distribution In A Vertically Integrated Circuit 有权
标题翻译：垂直集成电路中的配电
公开(公告)号：US20100140808A1
公开(公告)日：2010-06-10
申请号：US12703365
申请日：2010-02-10
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L21/6835 , H01L23/481 , H01L23/5286 , H01L25/0657 , H01L2221/68363 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
摘要翻译：第一通孔与周围的晶片基板材料电绝缘。第二通孔不与周围的晶片基板材料电绝缘。当非绝缘通孔用作Vdd或GND的路径时，这种配置是有利的。通过不使通孔绝缘，允许第一电源电压（Vdd或GND）流过周围的晶片基板材料，从而降低第一电源电压路径的电阻。

10. 发明申请

US20090111214A1 Method for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit 有权
标题翻译：三维垂直集成电路中功率分配改进方法
公开(公告)号：US20090111214A1
公开(公告)日：2009-04-30
申请号：US11928181
申请日：2007-10-30
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L21/60
CPC分类号： H01L21/6835 , H01L23/481 , H01L23/5286 , H01L25/0657 , H01L2221/68363 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
摘要翻译：第一通孔与周围的晶片基板材料电绝缘。第二通孔不与周围的晶片基板材料电绝缘。当非绝缘通孔用作Vdd或GND的路径时，这种配置是有利的。通过不使通孔绝缘，允许第一电源电压（Vdd或GND）流过周围的晶片基板材料，从而降低第一电源电压路径的电阻。

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