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1. 发明授权

US4522845A Process for producing a layer of a metal silicide by applying multichromatic radiation 失效
标题翻译：通过施加多层辐射来制造金属硅化物层的方法
公开(公告)号：US4522845A
公开(公告)日：1985-06-11
申请号：US505678
申请日：1983-06-20
申请人： Ronald A. Powell , Ronald T. Fulks
发明人： Ronald A. Powell , Ronald T. Fulks
IPC分类号： C01B33/06 , C23C14/06 , C23C16/42 , H01L21/28 , H01L21/285 , H01L21/324
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/28518 , Y10S148/004 , Y10S148/14
摘要： Multichromatic radiation is applied rapidly to silicon or polysilicon placed in contact with a silicide-forming metal to form metal silicide having low resistivity without deleterious later diffusion of dopants in adjacent single crystal or polysilicon. The radiation is applied to a metal deposited on silicon or to a metal codeposited with or to silicide deposited from a metal-Si composite target. The temperatures preferably rise to between 600.degree. C. and 1200.degree. C. and the total heating periods are less than about one minute, with 10 to 30 seconds being typical.
摘要翻译：将多色辐射快速地施加到与形成硅化物的金属接触的硅或多晶硅，以形成具有低电阻率的金属硅化物，而不会在相邻的单晶或多晶硅中稍后扩散掺杂剂。将辐射施加到沉积在硅上的金属或与由金属-Si复合靶沉积的金属共沉积的金属上。温度优选升高至600℃至1200℃，总加热时间小于约1分钟，典型值为10至30秒。

2. 发明申请

US20120080793A1 SUBTRACTIVE PATTERNING TO DEFINE CIRCUIT COMPONENTS 有权
标题翻译：定义电路组件的描述性方案
公开(公告)号：US20120080793A1
公开(公告)日：2012-04-05
申请号：US13251446
申请日：2011-10-03
申请人： Michal Danek , Juwen Gao , Ronald A. Powell , Aaron R. Fellis
发明人： Michal Danek , Juwen Gao , Ronald A. Powell , Aaron R. Fellis
IPC分类号： H01L23/48 , H01L21/28 , H01L21/768
CPC分类号： H01L21/76876 , H01L21/28562 , H01L21/76885 , H01L21/76895 , H01L23/53261 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.
摘要翻译：某些实施例涉及由钨或其它导电材料的覆盖层的消减图案形成的局部互连。钨或其他沉积金属的晶粒尺寸可以生长到相对较大的尺寸，这导致增加的导电性，这是由于例如当电子在传导期间从一个晶粒移动到下一个晶粒时在晶界处的电子散射减小。

3. 发明授权

US06709557B1 Sputter apparatus for producing multi-component metal alloy films and method for making the same 有权
标题翻译：用于制造多组分金属合金膜的溅射装置及其制造方法
公开(公告)号：US06709557B1
公开(公告)日：2004-03-23
申请号：US10085361
申请日：2002-02-28
申请人： Sridhar K. Kailasam , Ronald A. Powell , E. Derryck Settles
发明人： Sridhar K. Kailasam , Ronald A. Powell , E. Derryck Settles
IPC分类号： C23C1435
CPC分类号： H01J37/3429 , C23C14/3407
摘要： A mosaic or inlaid sputter target design suitable for conventional planar magnetron deposition, RF ionized physical vapor deposition, HCM ionized PVD, ionized metal plasma (IMP) deposition, or self-ionized plasma (SIP) deposition of multi-component alloys for use in integrated circuit metallization. Inlays are inserted within a planar sputter target in the shape of wedges, wires, or buttons to achieve uniform deposition of films on semiconductor substrates during sputtering. Metal alloy strips within a three-dimensional HCM target achieve the same uniform deposition. The deposition leads to the production of CuAl, CuBe, CuB, CuCd, CuCo, CuCr, CuIn, CuPd, CuSn, CuTa, CuTi, CuZr or CuZn alloy films deposited on the wafer. Non-copper films may also be deposited. The inlay-target adjoining surfaces may be machine stepped or tapered to limit wicking from the target backing material.
摘要翻译：镶嵌或镶嵌的溅射靶设计适用于传统的平面磁控管沉积，RF电离物理气相沉积，HCM离子化PVD，离子化金属等离子体（IMP）沉积或多组分合金的自离子等离子体（SIP）沉积，用于集成电路金属化。镶嵌在楔形，电线或按钮的形式的平面溅射靶内插入，以在溅射期间实现膜在半导体衬底上的均匀沉积。三维HCM靶内的金属合金条实现了相同的均匀沉积。沉积导致沉积在晶片上的CuAl，CuBe，CuB，CuCd，CuCo，CuCr，CuIn，CuPd，CuSn，CuTa，CuTi，CuZr或CuZn合金膜的生产。非铜膜也可以沉积。镶嵌目标邻接表面可以是机器台阶或锥形以限制来自目标背衬材料的芯吸。

4. 发明授权

US06319842B1 Method of cleansing vias in semiconductor wafer having metal conductive layer 有权
标题翻译：在具有金属导电层的半导体晶片中清洁通孔的方法
公开(公告)号：US06319842B1
公开(公告)日：2001-11-20
申请号：US09753432
申请日：2001-01-02
申请人： Mukul Khosla , Lap Tam , Ronald A. Powell , Ronald D. Allen , Robert T. Rozbicki , Erich Klawuhn , E. Derryck Settles
发明人： Mukul Khosla , Lap Tam , Ronald A. Powell , Ronald D. Allen , Robert T. Rozbicki , Erich Klawuhn , E. Derryck Settles
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76814 , Y10S438/906
摘要： Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semiconductor structure by creating a plasma to ionize the inert gas. The power applied to the plasma is preferably high enough to give the ions of the inert gas a high degree of directionality as they approach the structure. The first stage is continued until the non-volatile contaminants have been sufficiently removed from the structure. In the second stage, the power is reduced and the reducing gas (e.g., hydrogen) reacts with the oxides (e.g., copper oxide) to form elemental metal and water vapor. During the second stage there is no appreciable sputtering, and therefore the damage to the structure is limited as compared with processes that use sputtering and reduction simultaneously.
摘要翻译：在半导体处理中形成的非挥发性和氧化物残余物在两阶段工艺中从半导体结构中去除。将惰性气体和还原气体引入反应器。在第一阶段，通过产生等离子体以使惰性气体离子化，从半导体结构溅射非挥发性污染物。施加到等离子体的功率优选地足够高以使惰性气体的离子在接近结构时具有高度的方向性。第一阶段继续进行，直至非挥发性污染物从结构中充分除去。在第二阶段中，功率降低，并且还原气体（例如氢气）与氧化物（例如氧化铜）反应以形成元素金属和水蒸气。在第二阶段期间，没有明显的溅射，因此与使用溅射和还原的方法相比，对结构的损害是有限的。

5. 发明授权

US4661177A Method for doping semiconductor wafers by rapid thermal processing of solid planar diffusion sources 失效
标题翻译：通过固体平面扩散源的快速热处理来掺杂半导体晶片的方法
公开(公告)号：US4661177A
公开(公告)日：1987-04-28
申请号：US785418
申请日：1985-10-08
申请人： Ronald A. Powell
发明人： Ronald A. Powell
IPC分类号： H01L21/22 , H01L21/223 , H01L21/225 , H01L21/268 , H01L21/3215 , H01L21/383
CPC分类号： H01L21/223 , H01L21/2254 , H01L21/2255 , H01L21/2686 , H01L21/32155 , Y10S148/004
摘要： Doping of a semiconductor wafer is accomplished by placing the wafer in close proximity to a solid planar dopant source and rapidly heating the combination to a high temperature for a short time in a rapid thermal processing apparatus.
摘要翻译：半导体晶片的掺杂通过将晶片放置在靠近固体平面掺杂剂源并且在快速热处理设备中将该组合在短时间内快速加热到高温来实现。

6. 发明授权

US06790773B1 Process for forming barrier/seed structures for integrated circuits 有权
标题翻译：用于形成用于集成电路的屏障/种子结构的工艺
公开(公告)号：US06790773B1
公开(公告)日：2004-09-14
申请号：US10232445
申请日：2002-08-28
申请人： John S. Drewery , Ronald A. Powell
发明人： John S. Drewery , Ronald A. Powell
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
摘要翻译：提供了一种工艺和结构，其允许电镀使用介电层和可镀层之间的非保形导电层来填充亚微米高的纵横比特征。导电层是覆盖晶片的平面表面和要填充的特征的底部的相对较厚的层。在特征侧壁上形成很少或者没有导电层的材料。场上的厚导电层为均匀电镀提供了足够的导电性，同时侧壁上不存在显着的导电材料会降低特征的纵横比，并使电镀更容易实现无空隙填充。此外，在侧壁上不存在显着的材料允许形成更厚的阻挡层以获得更高的可靠性。

7. 发明授权

US06589887B1 Forming metal-derived layers by simultaneous deposition and evaporation of metal 有权
标题翻译：通过金属的同时沉积和蒸发形成金属衍生层
公开(公告)号：US06589887B1
公开(公告)日：2003-07-08
申请号：US09975612
申请日：2001-10-11
申请人： Jeremie Dalton , Ronald A. Powell , Sridhar K. Kailasam , Sasangan Ramanathan
发明人： Jeremie Dalton , Ronald A. Powell , Sridhar K. Kailasam , Sasangan Ramanathan
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , C23C14/04 , C23C14/18 , H01L21/2855 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76831 , H01L21/76865 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.
摘要翻译：本发明涉及在基材上形成金属衍生层的方法。优选的方法适用于集成电路制造。特别地，可以使用选择性方法在部分制造的集成电路上形成扩散阻挡层。在一个优选的方法中，将晶片加热并暴露于金属蒸气。在特定条件下，金属蒸汽与电介质表面反应形成扩散阻挡层，但不与金属表面反应。因此，本发明的方法形成了选择性地保护电介质表面但留下没有扩散阻挡层的金属表面的扩散阻挡层。

8. 发明授权

US06541374B1 Method of depositing a diffusion barrier for copper interconnection applications 有权
标题翻译：沉积用于铜互连应用的扩散阻挡层的方法
公开(公告)号：US06541374B1
公开(公告)日：2003-04-01
申请号：US09965471
申请日：2001-09-26
申请人： Tarek Suwwan de Felipe , Michal Danek , Erich Klawuhn , Ronald A. Powell
发明人： Tarek Suwwan de Felipe , Michal Danek , Erich Klawuhn , Ronald A. Powell
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/76813 , H01L21/76856
摘要： The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.
摘要翻译：本发明涉及在集成电路制造的上下文中形成扩散阻挡层的方法。本发明的方法允许在具有暴露的导体和电介质区域的部分制造的集成电路上选择性地沉积金属氮化物阻挡层材料，并且将金属氮化物阻挡材料转化成具有低通孔电阻的有效扩散阻挡层。在使用TiN的优选方法中，通过控制CVD工艺条件来实现单个阻挡层沉积中的微分形态。据信，沉积在导体上的TiN的绝对量不降低，但是形态发生变化，使得阻挡层形成后的通孔电阻几乎不增加或没有增加。本发明还涉及由应用所述方法产生的新型集成电路结构。

9. 发明授权

US08053861B2 Diffusion barrier layers 有权
标题翻译：扩散阻挡层
公开(公告)号：US08053861B2
公开(公告)日：2011-11-08
申请号：US12359997
申请日：2009-01-26
申请人： Thomas W. Mountsier , Roey Shaviv , Steven T. Mayer , Ronald A. Powell
发明人： Thomas W. Mountsier , Roey Shaviv , Steven T. Mayer , Ronald A. Powell
IPC分类号： H01L21/70
CPC分类号： C23C14/0623 , C23C14/06 , C23C14/3414 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76898 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.
摘要翻译：提供了用于沉积阻挡层的方法和装置，用于阻挡导电材料从集成电路中的导电线扩散到电介质材料中。阻挡层可以含有铜。在一些实施例中，这些层具有足够的导电性，用于直接电镀导电材料，而不需要中间种子层。这样的阻挡层可以与小于65nm宽的电路线并且在某些实施例中小于40nm宽使用。阻挡层可以被钝化以形成容易去除的层，包括层中的材料的硫化物，硒化物和/或碲化物。

10. 发明授权

US06464779B1 Copper atomic layer chemical vapor desposition 有权
标题翻译：铜原子层化学气相沉积
公开(公告)号：US06464779B1
公开(公告)日：2002-10-15
申请号：US09766143
申请日：2001-01-19
申请人： Ronald A. Powell , James A. Fair
发明人： Ronald A. Powell , James A. Fair
IPC分类号： C30B2902
CPC分类号： C23C16/45525 , C23C16/18 , C23C16/56 , C30B25/02 , C30B29/02
摘要： This invention pertains to systems and methods for atomic layer chemical vapor deposition. More specifically, the invention pertains to methods for copper atomic layer chemical vapor deposition, particularly to deposit a seed layer prior to the electrochemical Cu fill operation in integrated circuit fabrication. It also pertains to apparatus modules for performing such deposition.
摘要翻译：本发明涉及原子层化学气相沉积的系统和方法。更具体地，本发明涉及铜原子层化学气相沉积的方法，特别是在集成电路制造中的电化学Cu填充操作之前沉积种子层。它也涉及用于进行这种沉积的装置模块。

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