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1. 发明授权

US5734594A Method and system for enhancement of wafer alignment accuracy 失效
标题翻译：提高晶圆对准精度的方法和系统
公开(公告)号：US5734594A
公开(公告)日：1998-03-31
申请号：US719384
申请日：1996-09-25
申请人： Ron-Fu Chu , Zadig Cheung-Ching Lam
发明人： Ron-Fu Chu , Zadig Cheung-Ching Lam
IPC分类号： G03F9/00 , G01B7/00
CPC分类号： G03F9/70
摘要： This computer system, as well as its method of operation, corrects the position data used to define the location of alignment marks on a workpiece. The first step is to scan marks along a first direction to determine the direction of wafer scaling along the first direction. Second, scan marks along a second direction to determine the direction of wafer scaling along the second direction. Next, scan a first set of alignment marks on a workpiece oriented in a first direction and a second set of alignment marks on the workpiece oriented in a second direction in an initial sequence to collect initial direction data on the location. Then, scan the first set of alignment marks and the second set of alignment marks in a reverse sequence to collect reverse direction data on the location. Finally, average the initial direction data and the reverse direction data. This enables correction of false alignment data attributable to falsely measured locations of alignment marks.
摘要翻译：该计算机系统及其操作方法校正用于定义工件上对准标记位置的位置数据。第一步是沿着第一方向扫描标记，以确定沿着第一方向的晶片缩放的方向。其次，沿着第二方向扫描标记以确定沿着第二方向的晶片缩放的方向。接下来，扫描沿着第一方向定向的工件上的第一组对准标记，以及以初始顺序在第二方向上取向的工件上的第二组对准标记，以收集位置上的初始方向数据。然后，以相反的顺序扫描第一组对准标记和第二组对准标记，以收集位置上的反向数据。最后，平均初始方向数据和反向数据。这使得能够校正归因于对准标记的错误测量位置的错误对准数据。

2. 发明授权

US5582679A Enhanced metal etch process 失效
标题翻译：增强金属蚀刻工艺
公开(公告)号：US5582679A
公开(公告)日：1996-12-10
申请号：US304684
申请日：1994-09-12
申请人： Liu Lianjun , Ron-Fu Chu
发明人： Liu Lianjun , Ron-Fu Chu
IPC分类号： C23F4/00 , H01L21/3213 , H01L21/336
CPC分类号： C23F4/00 , H01L21/32135
摘要： A method for dry etching metal films, specifically aluminum, is described. This process uses photoresist as a mask with a gas mixture of BCl3, Cl2 and N2 used for the RIE. The addition of specific amounts of N2 to the etching chemistry results in non-tapered or non-undercut aluminum shapes. These desired shapes are attributed to the creation of polymer on the sidewall of the aluminum during the etching procedure, thus protecting against the isotropic components of RIE process, which cause the tapering. This RIE process can also be conducted at high enough temperatures, needed to avoid deleterious microloading effects.
摘要翻译：描述了用于干蚀刻金属膜，特别是铝的方法。该方法使用光刻胶作为掩模，用于用于RIE的BCl3，Cl2和N2的气体混合物。将特定量的N 2添加到蚀刻化学品中导致非锥形或非底切的铝形状。这些期望的形状归因于在蚀刻过程期间在铝的侧壁上产生聚合物，从而防止RIE工艺的各向同性组分引起锥形化。该RIE工艺也可以在足够高的温度下进行，以避免有害的微载荷效应。

3. 发明授权

US5496666A Contact hole mask for semiconductor fabrication 失效
标题翻译：用于半导体制造的接触孔掩模
公开(公告)号：US5496666A
公开(公告)日：1996-03-05
申请号：US329887
申请日：1994-10-27
申请人： Ron-Fu Chu , Chun H. Yik
发明人： Ron-Fu Chu , Chun H. Yik
IPC分类号： G03F1/00 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70433
摘要： This invention provides an improved process latitude mask for forming contact or via hole openings in a photoresist masking layer in the fabrication of semiconductor integrated circuits. The invention also provides a method of forming contact or via hole openings in a photoresist masking layer using an improved process latitude mask. The improved process latitude mask, called a dot mask, uses an opaque blocking area formed in the center of the primary opening in a projection mask for forming contact or via hole openings in a photoresist layer. The opaque blocking area is equal to or less than the area of the primary opening divided by nine. The opaque blocking area is small enough so that it will not form an image in the photoresist layer. The opaque blocking area modifies the light intensity profile at the photoresist layer in a manner which improves process latitude.
摘要翻译：本发明提供了一种用于在半导体集成电路的制造中在光致抗蚀剂掩模层中形成接触或通孔开口的改进的工艺纬度掩模。本发明还提供了使用改进的工艺纬度掩模在光致抗蚀剂掩模层中形成接触孔或通孔开口的方法。称为点阵掩模的改进的工艺纬度掩模使用在投影掩模中形成在主开口的中心的不透明阻挡区域，用于在光致抗蚀剂层中形成接触或通孔开口。不透明阻挡区域等于或小于主开口面积除以9。不透明阻挡区域足够小，使得其不会在光致抗蚀剂层中形成图像。不透明阻挡区域以改善工艺纬度的方式改变光致抗蚀剂层处的光强度分布。

4. 发明授权

US06696227B2 Shift multi-exposure method 有权
标题翻译：移位多曝光法
公开(公告)号：US06696227B2
公开(公告)日：2004-02-24
申请号：US10016893
申请日：2001-12-13
申请人： Chung-Wei Hsu , Ron-Fu Chu
发明人： Chung-Wei Hsu , Ron-Fu Chu
IPC分类号： G03F720
CPC分类号： G03F7/70466
摘要： The present invention provides a shift multi-exposure method for defining a regular pattern by a photomask. The method comprises the following steps. First, a photoresist layer comprising a first region and a second region is formed on a substrate. Then, a first pattern is defined on the first region by the photomask. Next, the photomask is moved a predetermined distance, and a second pattern is defined on the second region by the photomask. Finally, development is performed to display the first pattern and the second pattern on the photoresist layer.
摘要翻译：本发明提供一种用于通过光掩模定义规则图案的偏移多曝光方法。该方法包括以下步骤。首先，在基板上形成包括第一区域和第二区域的光致抗蚀剂层。然后，通过光掩模在第一区域上定义第一图案。接下来，将光掩模移动预定距离，并且通过光掩模在第二区域上限定第二图案。最后，进行显影以在光致抗蚀剂层上显示第一图案和第二图案。

5. 发明授权

US06451706B1 Attenuation of reflecting lights by surface treatment 失效
标题翻译：表面处理反射灯衰减
公开(公告)号：US06451706B1
公开(公告)日：2002-09-17
申请号：US08657219
申请日：1996-06-03
申请人： Ron-Fu Chu , Yang Pan , Qun Ying Lin , Mei Sheng Zhou
发明人： Ron-Fu Chu , Yang Pan , Qun Ying Lin , Mei Sheng Zhou
IPC分类号： H01L21302
CPC分类号： H01L21/32137 , G03F7/091 , H01L21/0276 , H01L21/32139
摘要： A new method of avoiding resist notching in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device is described. Bare active areas are provided surrounded by field oxide isolation on a semiconductor substrate wherein the surface of the substrate has an uneven topography due to the uneven interface between the active areas and the isolation. A polysilicon layer is deposited over the active areas and the field oxide isolation of the substrate. The surface of the polysilicon layer is roughened using a plasma etching process wherein pits are formed on the surface which act as light traps. The roughened polysilicon layer is covered with a layer of photoresist. Portions of the photoresist layer are exposed to actinic light wherein reflection lights from the actinic light are trapped in the pits. The reflection lights do not reflect onto the unexposed portion of the photoresist layer. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer wherein the absence of reflection lights reflecting onto the unexposed portion of the photoresist results in the notch-free photoresist mask in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device.
摘要翻译：描述了在集成电路器件的制造中避免形成多晶硅栅电极时的抗蚀刻缺口的新方法。在半导体衬底上围绕场氧化物隔离提供裸露的有源区域，其中由于有源区域与隔离之间的不平坦界面，衬底的表面具有不平坦的形貌。多晶硅层沉积在有源区和衬底的场氧化物隔离之上。使用等离子体蚀刻工艺将多晶硅层的表面粗糙化，其中在作为光阱的表面上形成有凹坑。粗糙多晶硅层被一层光致抗蚀剂覆盖。光致抗蚀剂层的一部分暴露于光化光，其中来自光化光的反射光被捕获在凹坑中。反射光不会反射到光致抗蚀剂层的未曝光部分上。光致抗蚀剂层被显影和图案化以形成用于多晶硅层的期望的光致抗蚀剂掩模，其中反射到光致抗蚀剂的未曝光部分上的反射光的不存在导致在制造中形成多晶硅栅电极的无切口光致抗蚀剂掩模的集成电路装置。

6. 发明授权

US6139251A Stepper alignment method and apparatus 有权
标题翻译：步进对准方法和装置
公开(公告)号：US6139251A
公开(公告)日：2000-10-31
申请号：US236359
申请日：1999-01-25
申请人： Ron-Fu Chu
发明人： Ron-Fu Chu
IPC分类号： H01L21/68 , H01L21/683 , B65G47/24
CPC分类号： H01L21/682 , H01L21/6838 , Y10S414/136
摘要： A stepper alignment method and apparatus for transferring circuit layout on a mask to a wafer precisely includes a stepper located in a susceptor and includes a vacuum chuck and a movable vacuum chuck. The wafer has two notches on its perimeter. The vacuum chuck has two sets of photo sensors mating against the notches and a central circular opening for housing the movable vacuum chuck therein. The movable vacuum chuck holds the wafer by means of vacuum force and is able to rotate and move linearly to align the notches of the wafer against the photo sensors accurately at high speed.
摘要翻译：用于将掩模上的电路布局传送到晶片的步进对准方法和装置精确地包括位于基座中的步进器，并且包括真空卡盘和可动真空卡盘。晶圆在其周边有两个凹口。真空吸盘具有与凹口配合的两组光传感器和用于将可动真空吸盘容纳在其中的中心圆形开口。可移动的真空吸盘通过真空力保持晶片，并且能够线性地旋转和移动，以使晶片的凹口以高速精确地对准光敏传感器。

7. 发明授权

US5795699A Langmuir-blodgett (LB) films as ARC and adhesion promoters for patterning of semiconductor devices 失效
标题翻译： Langmuir-blodgett（LB）膜作为ARC和用于图案化半导体器件的粘合促进剂
公开(公告)号：US5795699A
公开(公告)日：1998-08-18
申请号：US679858
申请日：1996-07-15
申请人： Mei Sheng Zhou , Ron-Fu Chu
发明人： Mei Sheng Zhou , Ron-Fu Chu
IPC分类号： G03F7/09 , G03F7/16 , G03C5/00
CPC分类号： G03F7/091 , G03F7/165 , Y10S438/939
摘要： A method for forming upon a reflective layer, such as a reflective conducting layer, within an integrated circuit an Anti-Reflective Coating (ARC) which simultaneously possesses adhesion promotion characteristics for an organic layer to be formed upon the reflective layer. There is first formed upon a semiconductor wafer a reflective integrated circuit layer which may be a hydrophilic reflective integrated circuit layer or a hydrophobic integrated circuit layer. The semiconductor wafer is then immersed into and withdrawn from a Langmuir trough having formed therein a Langmuir-Blodgett (LB) monolayer film of a dye surfactant molecule ordered upon a surface of water. Upon withdrawing the wafer from the Langmuir trough, there is formed upon the reflective integrated circuit layer an ordered LB film of the dye surfactant molecule. The chromophore groups within the dye surfactant molecule and ordered LB film provide ARC characteristics to the reflective layer.
摘要翻译：一种用于在集成电路内的反射层（例如反射导电层）上形成抗反射涂层（ARC）的方法，该抗反射涂层同时具有将在反射层上形成的有机层的粘附促进特性。首先在半导体晶片上形成反射集成电路层，反射集成电路层可以是亲水反射集成电路层或疏水性集成电路层。然后将半导体晶片浸入Langmuir槽中并从Langmuir槽中取出，Langmuir槽中形成了在水表面上排列的染料表面活性剂分子的Langmuir-Blodgett（LB）单层膜。当从Langmuir槽中取出晶片时，在反射集成电路层上形成染料表面活性剂分子的有序LB膜。染料表面活性剂分子内的发色团和有序的LB膜为反射层提供ARC特性。

8. 发明授权

US06551520B1 Exhausting method and means in a dry etching apparatus 有权
标题翻译：干蚀刻装置中的排气方法和装置
公开(公告)号：US06551520B1
公开(公告)日：2003-04-22
申请号：US09589080
申请日：2000-06-08
申请人： Ron-Fu Chu
发明人： Ron-Fu Chu
IPC分类号： C23F100
CPC分类号： H01J37/32834 , H01J37/3244 , Y10T279/23
摘要： In a method for exhausting processing gases out of a dry etching apparatus, processing gases are introduced into a processing chamber of the dry etching apparatus and converted into a gas plasma to etch a semiconductor workpiece. After plasma etching the semiconductor workpiece, the gas plasma is centrally gathered under the semiconductor workpiece by a sucking force formed surrounding the bottom periphery of the semiconductor workpiece, and then, is exhausted. The semiconductor workpiece to be processed is placed on a chuck under which an exhausting means is arranged.
摘要翻译：在从干蚀刻装置排出处理气体的方法中，将处理气体引入到干蚀刻装置的处理室中，并转换成气体等离子体以蚀刻半导体工件。在等离子体蚀刻半导体工件之后，通过围绕半导体工件的底部周边形成的吸力将气体等离子体集中聚集在半导体工件的下方，然后被排出。待加工的半导体工件被放置在卡盘上，在该卡盘上布置排气装置。

9. 发明授权

US5863307A Method and slurry composition for chemical-mechanical polish (CMP) planarizing of copper containing conductor layers 失效
标题翻译：含铜导体层的化学机械抛光（CMP）平面化的方法和浆料组成
公开(公告)号：US5863307A
公开(公告)日：1999-01-26
申请号：US80804
申请日：1998-05-18
申请人： Mei Sheng Zhou , Ron-Fu Chu
发明人： Mei Sheng Zhou , Ron-Fu Chu
IPC分类号： C09K3/14 , H01L21/321 , H01L21/768 , B24D3/34
CPC分类号： H01L21/7684 , C09K3/1472 , H01L21/3212
摘要： A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.
摘要翻译：化学机械抛光（CMP）平面化方法和化学机械抛光（CMP）浆料组合物用于集成电路中铜金属和铜金属合金层的化学机械抛光（CMP）平面化。首先提供了在其表面上形成图案化衬底层的半导体衬底。形成在图案化衬底层的内部和之上的是铜层金属层或覆盖铜金属合金层。然后通过使用化学机械抛光（CMP）浆料组合物的化学机械抛光（CMP）平面化方法将橡皮布铜金属层或橡皮布铜金属合金层平坦化。化学机械抛光（CMP）浆料组合物包含非水配位溶剂和卤素原子产生物。

10. 发明授权

US5728493A Antireflection mask for contact hole opening 失效
标题翻译：用于接触孔开口的防反射罩
公开(公告)号：US5728493A
公开(公告)日：1998-03-17
申请号：US725809
申请日：1996-10-04
申请人： Chet Ping Lim , Ron-Fu Chu
发明人： Chet Ping Lim , Ron-Fu Chu
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/50
摘要： An antireflection mask and method of using the antireflection mask to form contact holes for an integrated circuit wafer are described. The antireflection mask has a patterned opaque layer formed on a transparent mask substrate. The patterned opaque layer has first openings for exposing photoresist in regions where the photoresist is thicker and second openings for exposing photoresist in regions where the photoresist is thinner. A patterned layer of antireflection material having a light transmittance of less than 100% is formed over the second openings but not over the first openings. Light is passed through the mask to expose a layer of photoresist. The light exposing the thinner photoresist regions is attenuated by the antireflection material thereby compensating for variations in photoresist thickness. In addition the antireflection material reduces reflections from the patterned opaque layer of the mask.
摘要翻译：描述了使用抗反射掩模形成用于集成电路晶片的接触孔的抗反射掩模和方法。抗反射掩模具有形成在透明掩模基板上的图案化不透明层。图案化的不透明层具有用于在光致抗蚀剂更厚的区域中曝光光致抗蚀剂的第一开口和用于在光刻胶更薄的区域中曝光光致抗蚀剂的第二开口。在第二开口上形成透光率小于100％的防反射材料的图案层，但不在第一开口上。光通过掩模曝光一层光致抗蚀剂。暴露更薄的光致抗蚀剂区域的光被抗反射材料衰减，从而补偿光致抗蚀剂厚度的变化。此外，抗反射材料减少了掩模的图案化不透明层的反射。

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