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1. 发明申请

US20090277670A1 High Density Printed Circuit Board Interconnect and Method of Assembly 审中-公开
标题翻译：高密度印刷电路板互连和组装方法
公开(公告)号：US20090277670A1
公开(公告)日：2009-11-12
申请号：US12118696
申请日：2008-05-10
申请人： Roger A. Booth, JR. , John R. Dangler , Matthew S. Doyle , Jesse M. Hefner , Thomas W. Liang , Ankur K. Patel , Paul W. Rudrud
发明人： Roger A. Booth, JR. , John R. Dangler , Matthew S. Doyle , Jesse M. Hefner , Thomas W. Liang , Ankur K. Patel , Paul W. Rudrud
IPC分类号： H05K1/02
CPC分类号： H05K1/142 , H05K3/325 , H05K3/365 , H05K2201/0314 , H05K2201/09845 , H05K2201/10378 , H05K2201/10598
摘要： A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board.
摘要翻译：提供了具有接合第一和第二子电路板的边缘的印刷电路板组件。第一子电路板包括具有阶梯轮廓互连的边缘，其中轮廓上的每个楼梯暴露信号层的区域。信号层的每个曝光部分在其上具有多个信号焊盘。第二子电路板包括具有逆阶梯轮廓互连的边缘。衬垫焊盘连接器位于每个子电路板之间并且电互连每个子电路板上的各个信号层。

2. 发明申请

US20120184073A1 PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE 有权
标题翻译：可编程高K /金属栅存储器件
公开(公告)号：US20120184073A1
公开(公告)日：2012-07-19
申请号：US13433423
申请日：2012-03-29
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译：提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和半导体衬底上的第二金属栅电极。在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质到第二金属栅电极的侧壁。

3. 发明申请

US20110215321A1 POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC 有权
标题翻译：用于与金属栅和高K电介质集成的多晶硅电阻器和电子熔断器
公开(公告)号：US20110215321A1
公开(公告)日：2011-09-08
申请号：US12719289
申请日：2010-03-08
申请人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
IPC分类号： H01L29/12 , H01L21/02 , H01L21/768 , H01L29/86 , H01L23/525
CPC分类号： H01L21/02 , H01L21/768 , H01L23/525 , H01L29/12 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.
摘要翻译：提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域，掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

4. 发明申请

US20090242953A1 SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE 有权
标题翻译：与高K /金属闸门兼容的低压电容器
公开(公告)号：US20090242953A1
公开(公告)日：2009-10-01
申请号：US12059174
申请日：2008-03-31
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/0629
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

5. 发明申请

US20120061798A1 HIGH CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：高电容式电容器
公开(公告)号：US20120061798A1
公开(公告)日：2012-03-15
申请号：US12881481
申请日：2010-09-14
申请人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
发明人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.
摘要翻译：双节点介质沟槽电容器包括在沟槽中形成的一叠层。层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

6. 发明申请

US20100200949A1 METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE 审中-公开
标题翻译：用于调节金属栅极和高K器件的阈值电压的方法
公开(公告)号：US20100200949A1
公开(公告)日：2010-08-12
申请号：US12370024
申请日：2009-02-12
申请人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L27/0605 , H01L27/0733 , H01L27/1203 , H01L28/90 , H01L29/66181
摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.
摘要翻译：形成深沟槽电容器的方法包括提供晶片。器件形成在晶片的前侧。在晶片的基板上形成贯通硅通孔。深沟槽形成在晶片的背面。在深沟槽中形成深沟槽电容器。直通硅通孔将深沟槽电容器连接到器件。

7. 发明申请

US20100032732A1 ELECTRICAL ANTIFUSE HAVING A MULTI-THICKNESS DIELECTRIC LAYER 有权
标题翻译：具有多层电介质层的电抗体
公开(公告)号：US20100032732A1
公开(公告)日：2010-02-11
申请号：US12187003
申请日：2008-08-06
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
IPC分类号： H01L29/78 , H01L21/336 , H01L23/525
CPC分类号： H01L23/5252 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
摘要翻译：包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程电极，即晶体管的主体和栅电极，跨过栅极电介质。

8. 发明申请

US20090001464A1 FINFET WITH TOP BODY CONTACT 失效
标题翻译： FINFET与身体接触
公开(公告)号：US20090001464A1
公开(公告)日：2009-01-01
申请号：US11769032
申请日：2007-06-27
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855
摘要： FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin.
摘要翻译： FinFET在半导体鳍片的顶表面上设有主体接触。顶部本体接触可以相对于半导体鳍片和源极和漏极区域自对准。或者，源极和漏极区域可以形成为从半导体鳍片的顶表面凹陷。主体或身体的延伸部可以在通道上方或者源极和漏极区域之上接触。通过源极和漏极区域从半导体鳍片的顶表面的凹陷来避免源极和漏极与主体接触之间的电短路。

9. 发明申请

US20130147007A1 DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板上的深度隔离结构和深度电容器
公开(公告)号：US20130147007A1
公开(公告)日：2013-06-13
申请号：US13316104
申请日：2011-12-09
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L27/1087 , H01L27/10829 , H01L27/1203 , H01L29/945
摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
摘要翻译：在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。在沟槽中形成不透氧层和填充材料层。从第一沟槽内去除填充材料层和不透氧层。执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

10. 发明申请

US20120133023A1 THREE DIMENSIONAL INTEGRATED DEEP TRENCH DECOUPLING CAPACITORS 失效
标题翻译：三维集成深层解压电容器
公开(公告)号：US20120133023A1
公开(公告)日：2012-05-31
申请号：US13369460
申请日：2012-02-09
申请人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/92
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

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