专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090242953A1 SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE 有权
标题翻译：与高K /金属闸门兼容的低压电容器
公开(公告)号：US20090242953A1
公开(公告)日：2009-10-01
申请号：US12059174
申请日：2008-03-31
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/0629
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

2. 发明申请

US20090101956A1 EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE 有权
标题翻译：具有高K节点电介质和金属内电极的嵌入式电容器
公开(公告)号：US20090101956A1
公开(公告)日：2009-04-23
申请号：US11873728
申请日：2007-10-17
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01G4/00 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.
摘要翻译：在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。在半导体衬底中形成浅沟槽隔离结构。去除焊盘层之后，在器件区域中形成虚拟栅极结构。在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。虚拟结构被去除。深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极以及在器件区域中的高k栅极电介质和金属栅极。

3. 发明申请

US20090051002A1 ELECTRICAL FUSE HAVING A THIN FUSELINK 失效
标题翻译：电子保险丝
公开(公告)号：US20090051002A1
公开(公告)日：2009-02-26
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

4. 发明申请

US20100032732A1 ELECTRICAL ANTIFUSE HAVING A MULTI-THICKNESS DIELECTRIC LAYER 有权
标题翻译：具有多层电介质层的电抗体
公开(公告)号：US20100032732A1
公开(公告)日：2010-02-11
申请号：US12187003
申请日：2008-08-06
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
IPC分类号： H01L29/78 , H01L21/336 , H01L23/525
CPC分类号： H01L23/5252 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
摘要翻译：包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程电极，即晶体管的主体和栅电极，跨过栅极电介质。

5. 发明申请

US20120184073A1 PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE 有权
标题翻译：可编程高K /金属栅存储器件
公开(公告)号：US20120184073A1
公开(公告)日：2012-07-19
申请号：US13433423
申请日：2012-03-29
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译：提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和半导体衬底上的第二金属栅电极。在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质到第二金属栅电极的侧壁。

6. 发明申请

US20110215321A1 POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC 有权
标题翻译：用于与金属栅和高K电介质集成的多晶硅电阻器和电子熔断器
公开(公告)号：US20110215321A1
公开(公告)日：2011-09-08
申请号：US12719289
申请日：2010-03-08
申请人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
IPC分类号： H01L29/12 , H01L21/02 , H01L21/768 , H01L29/86 , H01L23/525
CPC分类号： H01L21/02 , H01L21/768 , H01L23/525 , H01L29/12 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.
摘要翻译：提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域，掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

7. 发明申请

US20130147007A1 DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板上的深度隔离结构和深度电容器
公开(公告)号：US20130147007A1
公开(公告)日：2013-06-13
申请号：US13316104
申请日：2011-12-09
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L27/1087 , H01L27/10829 , H01L27/1203 , H01L29/945
摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
摘要翻译：在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。在沟槽中形成不透氧层和填充材料层。从第一沟槽内去除填充材料层和不透氧层。执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

8. 发明申请

US20120068237A1 SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES 有权
标题翻译：用于嵌入式电容器和替换栅极器件的自对准带
公开(公告)号：US20120068237A1
公开(公告)日：2012-03-22
申请号：US12886224
申请日：2010-09-20
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.
摘要翻译：在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。通过平面化形成在每个栅电极上方的介电金属氧化物部分。电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

9. 发明申请

US20110272762A1 EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR 有权
标题翻译：嵌入式超薄型半导体绝缘体DRAM
公开(公告)号：US20110272762A1
公开(公告)日：2011-11-10
申请号：US12776829
申请日：2010-05-10
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ali Khakifirooz , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ali Khakifirooz , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66742 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.
摘要翻译：填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

10. 发明申请

US20120139080A1 METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE 有权
标题翻译：在绝缘体（SOI）衬底上形成半导体衬底接触的方法
公开(公告)号：US20120139080A1
公开(公告)日：2012-06-07
申请号：US12959824
申请日：2010-12-03
申请人： Geng Wang , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
发明人： Geng Wang , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
IPC分类号： H01L21/70 , H01L21/20
CPC分类号： H01L28/40 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/743 , H01L21/76224 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L28/91 , H01L29/0649 , H01L29/66181
摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
摘要翻译：提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。还提供了形成上述结构的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式