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1. 发明授权

US06321319B2 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 有权
公开(公告)号：US06321319B2
公开(公告)日：2001-11-20
申请号：US09756304
申请日：2001-01-08
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

2. 发明授权

US06243798B1 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 失效
标题翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的计算机系统
公开(公告)号：US06243798B1
公开(公告)日：2001-06-05
申请号：US08958940
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.
摘要翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上地址总线这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。

3. 发明授权

US6098160A Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效
标题翻译：用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
IPC分类号： G06F9/35 , G06F12/00
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译：一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

4. 发明授权

US06225678B1 Layout technique for a matching capacitor array using a continuous top electrode 有权
标题翻译：使用连续顶部电极的匹配电容器阵列的布局技术
公开(公告)号：US06225678B1
公开(公告)日：2001-05-01
申请号：US09221634
申请日：1998-12-23
申请人： Randy L. Yach , Igor Wojewoda
发明人： Randy L. Yach , Igor Wojewoda
IPC分类号： H01L2900
CPC分类号： H01L27/0805
摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
摘要翻译：匹配的电容器阵列在单个单片集成电路上实现。该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

5. 发明授权

US06593639B2 Layout technique for a capacitor array using continuous upper electrodes 有权
标题翻译：使用连续上电极的电容器阵列布局技术
公开(公告)号：US06593639B2
公开(公告)日：2003-07-15
申请号：US09846018
申请日：2001-04-30
申请人： Randy L. Yach , Igor Wojewoda
发明人： Randy L. Yach , Igor Wojewoda
IPC分类号： H01L2900
CPC分类号： H01L27/0805
摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
摘要翻译：匹配的电容器阵列在单个单片集成电路上实现。该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

6. 发明授权

US5812456A Switched ground read for EPROM memory array 失效
标题翻译： EPROM存储器阵列的开关地址读取
公开(公告)号：US5812456A
公开(公告)日：1998-09-22
申请号：US723927
申请日：1996-10-01
申请人： Richard Hull , Randy L. Yach
发明人： Richard Hull , Randy L. Yach
IPC分类号： G11C16/06 , G11C16/26 , G11C16/30 , G11C7/02
CPC分类号： G11C16/26 , G11C16/30
摘要： A technique for reading data from a selected memory element of an EPROM array having rows and columns with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element includes a transistor having gate, source and drain electrodes, and after selection of a particular memory element from which data is to be read by appropriately biasing the row and column associated with that memory element, the source electrode thereof is selectively connected to ground by a switching element to allow current flow through the source-drain path of the memory element and enable the readout of data therefrom after the drain and gate voltages of the memory element have stabilized.
摘要翻译：从具有可寻址存储元件的具有行和列的EPROM阵列的选定存储元件中读取数据的技术，其可以在行和列的相应交叉处有选择地访问。每个存储元件包括具有栅极，源极和漏极的晶体管，并且在通过适当地偏置与该存储元件相关联的行和列来选择要从其读取数据的特定存储元件之后，其源电极选择性地连接到通过开关元件接地以允许电流流过存储器元件的源极 - 漏极路径，并且在存储元件的漏极和栅极电压已经稳定之后能够从其读出数据。

7. 发明授权

US5454114A Microcontroller power-up delay 失效
标题翻译：微控制器上电延迟
公开(公告)号：US5454114A
公开(公告)日：1995-09-26
申请号：US238121
申请日：1994-04-04
申请人： Randy L. Yach , Sumit Mitra
发明人： Randy L. Yach , Sumit Mitra
IPC分类号： G06F1/04 , G06F1/24 , G06F11/267 , G06F15/78 , H03K17/22
CPC分类号： G06F1/24 , G06F11/221
摘要： A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.
摘要翻译：微控制器在操作时被调整为执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。微控制器包括用于在适合于其操作的预定范围内向总体设备供电的电源，以及用于以适于在设备内精确定时和计数的稳定性向微控制器提供时钟频率的时钟。微控制器被选择性地复位以防止其执行用于产生控制信号的程序和指令，并且尽管开始从复位状态移除直到电源提供的电源处于预定的状态时钟提供的时钟频率稳定。以这种方式，在实现器件稳定性之前，不允许微控制器的执行，以防止执行中的错误。在所公开的实施例中，复位条件由加电定时器和振荡器启动定时器维持，每个定时器具有可编程的超时间隔，以仅在两个定时器的超时间隔已经期满时才结束复位条件。

8. 发明授权

US07170136B2 High voltage ESD-protection structure 有权
公开(公告)号：US07170136B2
公开(公告)日：2007-01-30
申请号：US11201373
申请日：2005-08-10
申请人： Randy L. Yach , Greg Dix
发明人： Randy L. Yach , Greg Dix
IPC分类号： H01L23/62
CPC分类号： H01L27/0259
摘要： A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

9. 发明授权

US07002218B2 Low capacitance ESD-protection structure under a bond pad 有权
标题翻译：焊接垫下的低电容ESD保护结构
公开(公告)号：US07002218B2
公开(公告)日：2006-02-21
申请号：US10787387
申请日：2004-02-26
申请人： Randy L. Yach
发明人： Randy L. Yach
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , Y10S257/917
摘要： An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N− well is located substantially under the N+ and P+ diffusions. The surrounding N+ diffusion partially overlaps the edge of the N− well below it. An outer portion of the N+ diffusion, the portion overlapping the N− well, is within a P− well. Another N+ diffusion encircles the N+ diffusion surrounding the P+ diffusions. The another N+ diffusion is in the P− well and a field oxide may be located between the N+ diffusion and the another N+ diffusion. An NPN field transistor is formed with the N+ diffusion being the transistor collector, the P− well being the transistor base and the another N+ diffusion being the emitter.
摘要翻译： ESD保护结构基本上位于集成电路接合焊盘下方。该ESD保护结构通过在接合焊盘和ESD钳位电路之间插入正向二极管而形成为低电容结构。将ESD保护结构放在接合焊盘下方可消除寄生衬底电容，并利用由插入的正向偏置二极管形成的寄生PNP晶体管。 ESD保护结构包括基本上位于接合焊盘下方以进行ESD保护的相邻的交替P +和N +扩散。 P +扩散通过绝缘层与金属通孔连接到接合焊盘金属。 N +扩散与P +扩散相邻。 N +扩散围绕N +和P +扩散，并将N +扩散结合在一起，以便在每个P +扩散周围完全形成连续的N +扩散。 N阱基本上位于N +和P +扩散之下。周围的N +扩散与其下面的N阱的边缘部分重叠。 N +扩散的外部部分，与N阱重叠的部分在P-阱内。另外N +扩散围绕围绕P +扩散的N +扩散。另一个N +扩散在P-阱中，场氧化物可以位于N +扩散和另一个N +扩散之间。形成NPN场晶体管，其中N +扩散为晶体管集电极，P阱为晶体管基极，另一N +扩散为发射极。

10. 发明授权

US06208500B1 High quality factor capacitor 有权
标题翻译：高品质因素电容器
公开(公告)号：US06208500B1
公开(公告)日：2001-03-27
申请号：US09200542
申请日：1998-11-25
申请人： Sam E. Alexander , Randy L. Yach , Roger St. Amand
发明人： Sam E. Alexander , Randy L. Yach , Roger St. Amand
IPC分类号： H01G4005
CPC分类号： H01L28/40 , H01L27/0805
摘要： An improved high quality factor capacitive device is implemented on a single, monolithic integrated circuit. The new layout techniques improve the quality factor (Q) of the capacitor by reducing intrinsic resistance of the capacitor by reducing the distance between the metal contacts of the top and bottom conductive plates. The layout techniques require laying out the top conductive plate of the capacitor in strips such that metal contacts from the bottom conductive plate pass in between the strips and through the dielectric layer. Alternatively, the apertures may be etched into the top conductive plate so that metal contacts pass through the apertures and connect to the bottom conductive plate.
摘要翻译：改进的高品质因素电容器件在单个单片集成电路上实现。新的布局技术通过减小顶部和底部导电板的金属触点之间的距离来降低电容器的固有电阻，从而提高了电容器的品质因数（Q）。布局技术需要将带状电容器的顶部导电板布置成使得来自底部导电板的金属接触通过条带之间并通过介电层。或者，孔可以被蚀刻到顶部导电板中，使得金属触点穿过孔并连接到底部导电板。

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