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1. 发明授权

US6098160A Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效
标题翻译：用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
IPC分类号： G06F9/35 , G06F12/00
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译：一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

2. 发明申请

US20070283052A1 Dynamic Peripheral Function Remapping to External Input-Output Connections of an Integrated Circuit Device 有权
标题翻译：动态外设功能重新映射到集成电路器件的外部输入/输出连接
公开(公告)号：US20070283052A1
公开(公告)日：2007-12-06
申请号：US11686724
申请日：2007-03-15
申请人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
发明人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
IPC分类号： G06F3/00
CPC分类号： H03K19/17764 , H03K19/1732 , H03K19/17744
摘要： Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.
摘要翻译：通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。一个或多个外围输出功能可以映射到一个或多个外部输出连接。在同一输出连接上，同一输出功能可能同时处于活动状态。输出和输入可以被映射到具有或不具有输出的相同外部输入 - 输出连接，以便放置到非活动状态，例如高阻抗或开放式收集器。当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

3. 发明授权

US06985986B2 Variable cycle interrupt disabling 有权
公开(公告)号：US06985986B2
公开(公告)日：2006-01-10
申请号：US09870447
申请日：2001-06-01
申请人： Brian Boles , Joseph W. Triece , Joshua M. Conner
发明人： Brian Boles , Joseph W. Triece , Joshua M. Conner
IPC分类号： G06F13/24 , G06F9/44
CPC分类号： G06F13/24
摘要： A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.

4. 发明授权

US07634596B2 Dynamic peripheral function remapping to external input-output connections of an integrated circuit device 有权
标题翻译：动态外设功能重新映射到集成电路设备的外部输入 - 输出连接
公开(公告)号：US07634596B2
公开(公告)日：2009-12-15
申请号：US11686724
申请日：2007-03-15
申请人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
发明人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , H04L12/28
CPC分类号： H03K19/17764 , H03K19/1732 , H03K19/17744
摘要： Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.
摘要翻译：通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。一个或多个外围输出功能可以映射到一个或多个外部输出连接。在同一输出连接上，同一输出功能可能同时处于活动状态。输出和输入可以被映射到具有或不具有输出的相同外部输入 - 输出连接，以便放置到非活动状态，例如高阻抗或开放式收集器。当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

5. 发明授权

US07650440B2 Peripheral supplied addressing in a simple DMA module 有权
标题翻译：外设在简单的DMA模块中提供寻址
公开(公告)号：US07650440B2
公开(公告)日：2010-01-19
申请号：US11736348
申请日：2007-04-17
申请人： Steven Dawson , Willem Smit , Maria Smit, legal representative , Brian Boles
发明人： Steven Dawson , Willem Smit , Brian Boles
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.
摘要翻译：执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

6. 发明授权

US5861861A Microcontroller chip with integrated LCD control module and switched capacitor driver circuit 失效
标题翻译：具有集成LCD控制模块和开关电容驱动电路的微控制器芯片
公开(公告)号：US5861861A
公开(公告)日：1999-01-19
申请号：US671575
申请日：1996-06-28
申请人： James B. Nolan , Scott Ellison , Brian Boles , Rodney Drake , Russell E. Cooper
发明人： James B. Nolan , Scott Ellison , Brian Boles , Rodney Drake , Russell E. Cooper
IPC分类号： G02F1/133 , G06F3/147 , G09G3/00 , G09G3/18 , G09G3/36 , G09G5/00 , H02M3/07
CPC分类号： H02M3/07 , G06F3/147 , G09G3/18 , G09G3/006 , G09G3/3696 , G09G5/001
摘要： Apparatus for providing multiple of discrete voltage levels to drive a liquid crystal display (LCD) from an LCD module on board a microcontroller chip includes a charge pump with a switched-capacitor that develops the discrete voltages as multiples of the value of a base voltage that remains substantially without change irrespective of change in the supply voltage. A switched-capacitor charging circuit selectively charges a capacitor to produce successive additive charges individually retrievable from the capacitor. An LCD drive selectively transmits the discrete voltage levels to activate the LCD according to status of an external system under the control of the microcontroller. Voltage losses that may occur during the switched-capacitor charging are compensated to maintain the levels of the discrete voltages free of decay. Compensation is achieved by overcharging the capacitor by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feedback obtained from monitoring the charge on the capacitor.
摘要翻译：用于提供多个离散电压电平以从微控制器芯片上的LCD模块驱动液晶显示器（LCD）的装置包括具有开关电容器的电荷泵，其将离散电压开发为基本电压值的倍数无论电源电压的变化如何，均保持基本无变化。开关电容器充电电路选择性地对电容器充电以产生可从电容器单独检索的连续的附加电荷。 LCD驱动器根据微控制器的控制，根据外部系统的状态选择性地发送离散电压电平以激活LCD。在开关电容器充电期间可能发生的电压损耗被补偿以保持离散电压的电平没有衰减。通过使用从监视电容器上的电荷获得的有效反馈，使电容器过充电达到与电容器上的电压损失量相当的量。

7. 发明授权

US06552567B1 Functional pathway configuration at a system/IC interface 失效
标题翻译：功能通道在系统/ IC接口配置
公开(公告)号：US06552567B1
公开(公告)日：2003-04-22
申请号：US09964664
申请日：2001-09-28
申请人： Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
发明人： Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
IPC分类号： H03K190175
CPC分类号： G06F15/76
摘要： The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.
摘要翻译：本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

8. 发明授权

US5991196A Reprogrammable memory device with variable page size 失效
标题翻译：具有可变页面大小的可重复编程的存储器件
公开(公告)号：US5991196A
公开(公告)日：1999-11-23
申请号：US991423
申请日：1997-12-16
申请人： Joseph A. Thomsen , Timothy J. Phoenix , Brian Boles , Henry Pena , Gordon E. Luke
发明人： Joseph A. Thomsen , Timothy J. Phoenix , Brian Boles , Henry Pena , Gordon E. Luke
IPC分类号： G11C16/02 , G11C8/12 , G11C16/16 , G11C16/04
CPC分类号： G11C8/12 , G11C16/16
摘要： An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.
摘要翻译：改进的可再编程存储器件允许定义尺寸可变的存储器单元阵列内的页面，仅擦除所定义的可变页面中包含的数据，同时不影响存储器单元阵列中的剩余数据并重新编程定义的变量页。具有可变页大小的改进的可重编程存储器件包括其中存储器单元以行和列布置的存储器单元阵列; 地址解码逻辑，其耦合到用于访问存储器单元阵列的存储器单元阵列; 放大器逻辑耦合到存储器单元阵列，用于在访问存储器单元阵列时放大多个存储器单元和数据总线之间的电压电平; 列选择逻辑，其耦合到存储器单元阵列，用于确定来自存储器单元的阵列的选定行的哪个字被访问，并将多个存储器单元连接到放大器逻辑; 耦合到放大器逻辑的用于访问存储器单元阵列的控制信号; 以及耦合到地址解码逻辑的块使能信号，用于在待擦除的存储器单元阵列内改变页大小。

9. 发明申请

US20080028110A1 Peripheral Supplied Addressing In A Simple DMA 有权
标题翻译：外围提供的寻址在一个简单的DMA
公开(公告)号：US20080028110A1
公开(公告)日：2008-01-31
申请号：US11736348
申请日：2007-04-17
申请人： Steven Dawson , Willem Smit , Maria Smit , Brian Boles
发明人： Steven Dawson , Willem Smit , Maria Smit , Brian Boles
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.
摘要翻译：执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

10. 发明申请

US20050257016A1 Digital signal controller secure memory partitioning 审中-公开
标题翻译：数字信号控制器安全的内存分区
公开(公告)号：US20050257016A1
公开(公告)日：2005-11-17
申请号：US10846579
申请日：2004-05-17
申请人： Brian Boles , Sumit Mitra , Steven Marsh
发明人： Brian Boles , Sumit Mitra , Steven Marsh
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/1491
摘要： A controller offers various security modes for protecting program code and data stored in memory and ensuring that the protection is effective during all normal operating conditions of the controller. The controller includes configuration settings that segment program memory into a boot segment, a secure segment and a general segment, each with a particular level of security including no enhanced protection. The boot code segment (BS) is the most secure and may be used to store a secure boot loader. The secure code segment (SS) is useful for storing proprietary algorithms from third parties, such as algorithms for separating ambient noise from speech in speech recognition applications. The general code segment (GS) has the least security. The controller is configured to prevent program flow changes that would result in program code stored in high security segments from being accessed by program code stored in lower security segments. In addition, the processor may be configured to have associated secure data portions of both program memory, such as flash memory, and random access memory (RAM) corresponding to the BS, SS and GS. Attempts to read data from or write data to the program memory or RAM associated with a higher security level from a lower security level are prevented from occurring.
摘要翻译：控制器提供各种安全模式，用于保护存储在存储器中的程序代码和数据，并确保在控制器的所有正常操作条件下保护有效。控制器包括将程序存储器分割为引导段，安全段和通用段的配置设置，每个段具有特定级别的安全性，不包括增强的保护。启动代码段（BS）是最安全的，可用于存储安全引导加载程序。安全代码段（SS）用于存储来自第三方的专有算法，例如用于在语音识别应用中分离环境噪声与语音的算法。一般代码段（GS）的安全性最低。控制器被配置为防止程序流程改变，导致存储在高安全段中的程序代码被存储在较低安全段中的程序代码访问。此外，处理器可以被配置为具有诸如闪存之类的程序存储器和对应于BS，SS和GS的随机存取存储器（RAM）的相关联的安全数据部分。防止从较低安全级别读取数据或从与较高安全级别相关联的程序存储器或RAM写入数据的尝试发生。

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