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1. 发明授权

US08543888B2 Programmable cyclic redundancy check CRC unit 有权
标题翻译：可编程循环冗余校验CRC单元
公开(公告)号：US08543888B2
公开(公告)日：2013-09-24
申请号：US12776476
申请日：2010-05-10
申请人： Sudhir Bommena , Igor Wojewoda , Yong Yuenyongsgool , Vijay Dubey , Roshan Samuel , Jonathan Brant Ivey
发明人： Sudhir Bommena , Igor Wojewoda , Yong Yuenyongsgool , Vijay Dubey , Roshan Samuel , Jonathan Brant Ivey
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , H03M13/6516 , H03M13/6569
摘要： A cyclic redundancy check (CRC) unit has a programmable CRC engine, a variable buffer memory operable to store k words wherein each word has n-bits, wherein k and n can be varied, and shift logic operable to shift data from the variable buffer memory into the programmable CRC engine.
摘要翻译：循环冗余校验（CRC）单元具有可编程CRC引擎，可变缓冲存储器，可操作地存储k个字，其中每个字具有n位，其中k和n可以改变，并且移位逻辑可操作以从可变缓冲器内存进入可编程CRC引擎。

2. 发明申请

US20060020721A1 Configurable ping-pong buffers for USB buffer descriptor tables 审中-公开
标题翻译：用于USB缓冲区描述符表的可配置乒乓缓冲区
公开(公告)号：US20060020721A1
公开(公告)日：2006-01-26
申请号：US11075149
申请日：2005-03-08
申请人： Igor Wojewoda , Ross Fosler , Rawin Rojvanit
发明人： Igor Wojewoda , Ross Fosler , Rawin Rojvanit
IPC分类号： G06F3/06
CPC分类号： G06F13/38
摘要： A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping-pong buffer support mode, no hardware is required for automatic ping-pong buffer management. The Buffer Descriptor Tables may comprise a maximum of 128 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, each with at least one buffer descriptor, and each comprising four (4) memory locations. In the ping-pong buffer support for OUT endpoint 0 only mode, the buffer descriptor Tables may comprise a maximum of 132 memory locations, e.g., 16 OUT endpoints with an EVEN and an ODD endpoint 0, 16 IN endpoints, each with at least one descriptor, e.g., memory locations. This mode assures that endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. The Buffer Descriptor Tables may comprise a maximum of 256 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, an EVEN and ODD set for each, each with one descriptor, e.g., four (4) memory locations. This mode assures that all endpoint transfers may be serviced substantially without delay.
摘要翻译：一种数字设备，其具有用于在数字设备的USB接口中的USB通信缓冲器管理的可选模式。这些模式可以包括（1）不支持乒乓缓冲器支持，（2）对于某些端点的乒乓缓冲器支持，例如仅支持OUT端点0，以及（3）对所有端点的乒乓缓冲器支持。在无乒乓缓冲支持模式下，无需硬件自动乒乓缓冲区管理。缓冲器描述符表可以包括最多128个存储器位置，例如16个IN端点和16个OUT端点，每个具有至少一个缓冲器描述符，并且每个包括四（4）个存储器位置。在乒乓缓冲区支持OUT端点0的唯一模式下，缓冲区描述符表可以包含最多132个存储器位置，例如16个OUT端点，具有偶数和ODD端点0,16 IN端点，每个具有至少一个描述符，例如内存位置。该模式确保端点0建立传输可以无延迟地被服务，而仅需要缓冲器描述符的剩余部分的最小数量的存储器位置。在所有端点模式的乒乓缓冲区支持中，可以为所有端点提供自动乒乓缓冲区管理。缓冲器描述符表可以包括最多256个存储器位置，例如16个IN端点和16个OUT端点，为每个存储器单元设置一个EVEN和ODD，每个具有一个描述符，例如四（4）个存储器位置。该模式确保所有端点传输可以在没有延迟的情况下实际进行维护。

3. 发明授权

US06321319B2 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 有权
公开(公告)号：US06321319B2
公开(公告)日：2001-11-20
申请号：US09756304
申请日：2001-01-08
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

4. 发明授权

US5958039A Master-slave latches and post increment/decrement operations 失效
标题翻译：主从锁存和后递增/递减操作
公开(公告)号：US5958039A
公开(公告)日：1999-09-28
申请号：US958939
申请日：1997-10-28
申请人： Stephen Allen , Igor Wojewoda
发明人： Stephen Allen , Igor Wojewoda
IPC分类号： G06F9/42 , G06F7/78 , G06F9/32 , G06F9/38 , G06F12/02 , G11C8/00
CPC分类号： G06F7/785 , G06F9/321 , G06F9/3814 , G06F9/3867
摘要： The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.
摘要翻译：堆栈指针用于在堆栈存储器件中产生下一个未使用的位置，以指示要写入程序计数器中的当前值的位置。为了读取写入堆栈存储器件的程序计数器的最后一个值，堆栈指针还会向下一个未使用位置生成一个直接的前一个位置。堆栈指针将选择堆栈存储器设备中的下一个未使用的位置进行写入操作，并且在堆栈存储器设备中的下一个未使用位置的直接前一位置进行读取操作。在执行当前指令之后，堆栈指针将进一步对堆栈存储器设备中的下一未使用位置执行后递增或后递减操作。

5. 发明申请

US20130080819A1 MICROCONTROLLER WITH SCHEDULING UNIT 有权
标题翻译：带调度单元的微控制器
公开(公告)号：US20130080819A1
公开(公告)日：2013-03-28
申请号：US13247489
申请日：2011-09-28
申请人： Stephen Bowling , Igor Wojewoda
发明人： Stephen Bowling , Igor Wojewoda
IPC分类号： G06F1/14
CPC分类号： G06F1/14 , G06F1/3243 , G06F1/3287 , G06F15/7814 , G06F15/7853 , Y02D10/152 , Y02D10/171
摘要： A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.
摘要翻译：微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有：由独立时钟信号计时的定时器; 比较器，与所述定时器的定时器寄存器耦合并具有产生输出信号的输出; 与所述比较器耦合的事件寄存器; 增量时间寄存器以及由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器和输出与事件寄存器耦合。

6. 发明授权

US07634596B2 Dynamic peripheral function remapping to external input-output connections of an integrated circuit device 有权
标题翻译：动态外设功能重新映射到集成电路设备的外部输入 - 输出连接
公开(公告)号：US07634596B2
公开(公告)日：2009-12-15
申请号：US11686724
申请日：2007-03-15
申请人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
发明人： Igor Wojewoda , Brian Boles , Steve Bradley , Gaurang Kavaiya
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , H04L12/28
CPC分类号： H03K19/17764 , H03K19/1732 , H03K19/17744
摘要： Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.
摘要翻译：通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。一个或多个外围输出功能可以映射到一个或多个外部输出连接。在同一输出连接上，同一输出功能可能同时处于活动状态。输出和输入可以被映射到具有或不具有输出的相同外部输入 - 输出连接，以便放置到非活动状态，例如高阻抗或开放式收集器。当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

7. 发明授权

US06225678B1 Layout technique for a matching capacitor array using a continuous top electrode 有权
标题翻译：使用连续顶部电极的匹配电容器阵列的布局技术
公开(公告)号：US06225678B1
公开(公告)日：2001-05-01
申请号：US09221634
申请日：1998-12-23
申请人： Randy L. Yach , Igor Wojewoda
发明人： Randy L. Yach , Igor Wojewoda
IPC分类号： H01L2900
CPC分类号： H01L27/0805
摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
摘要翻译：匹配的电容器阵列在单个单片集成电路上实现。该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

8. 发明授权

US6098160A Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效
标题翻译：用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
IPC分类号： G06F9/35 , G06F12/00
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译：一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

9. 发明授权

US08108708B2 Power optimization when using external clock sources 有权
标题翻译：使用外部时钟源时的电源优化
公开(公告)号：US08108708B2
公开(公告)日：2012-01-31
申请号：US11865148
申请日：2007-10-01
申请人： Tim Phoenix , Igor Wojewoda , Pavan Kumar Bandarupalli
发明人： Tim Phoenix , Igor Wojewoda , Pavan Kumar Bandarupalli
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc.
摘要翻译：通过将期望的时钟振荡器频率范围编程到数字设备的配置存储器中，数字设备的逻辑电路可以被偏置以在特定外部时钟频率范围上操作。此外，时钟源选择也可以编程到配置寄存器中。然后配置偏置电路，使得数字设备的内部逻辑将在期望的时钟振荡器频率范围内工作。可以使用非易失性存储器来存储配置存储器的内容，以便在数字设备掉电期间保持配置。非易失性存储器可以是可编程熔丝链路，电可擦除和可编程存储器（EEPROM），闪速存储器等。

10. 发明授权

US07589564B2 Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode 有权
标题翻译：在低功率模式下以及从低功率模式出来时保持输入和/或输出配置和数据状态的方法
公开(公告)号：US07589564B2
公开(公告)日：2009-09-15
申请号：US12030264
申请日：2008-02-13
申请人： Michael Simmons , Igor Wojewoda
发明人： Michael Simmons , Igor Wojewoda
IPC分类号： H03K19/094
CPC分类号： G06F1/3203 , G06F1/24
摘要： A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.
摘要翻译：半导体集成电路器件在从低功率模式退出时，唤醒并重新初始化逻辑电路，以便恢复内部寄存器的先前逻辑状态，而不会干扰当前存在的输入输出（I / O）配置控制和数据状态输入低功耗模式。因此，在低功率模式下，不能分配连接到半导体集成电路器件的其它器件的操作。一旦半导体集成电路器件的所有内部逻辑和寄存器被重新初始化，就可能发出“低功率状态唤醒和恢复”信号。该信号表示在集成电路器件进入低功率模式时存储在I / O保持器单元中的I / O配置控制和数据状态已被恢复，并且可以将控制返回到逻辑电路和/或内部半导体集成电路器件的寄存器。

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