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1. 发明授权

US5578523A Method for forming inlaid interconnects in a semiconductor device 失效
标题翻译：在半导体器件中形成镶嵌互连的方法
公开(公告)号：US5578523A
公开(公告)日：1996-11-26
申请号：US444184
申请日：1995-05-18
申请人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein
发明人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/76802 , H01L21/76829 , H01L21/7685 , H01L21/76877 , Y10S438/959
摘要： In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.
摘要翻译：在本发明中，镶嵌互连（44）通过化学机械抛光形成。在层间电介质（30）和互连金属（42）之间形成呈氮化铝层形式的抛光辅助层（31），以防止在研磨时互连件的凹陷或凹陷。通过在抛光的最后阶段允许牺牲抛光辅助层（31）以与互连金属（42）相同的速率被去除，因此避免了凹陷。氮化铝层还通过为存在二氧化硅提供比铝更合适的成核位置，促进铝作为互连金属的化学气相沉积。

2. 发明授权

US5534462A Method for forming a plug and semiconductor device having the same 失效
标题翻译：用于形成插头的方法和具有该插头的半导体器件
公开(公告)号：US5534462A
公开(公告)日：1996-07-09
申请号：US393782
申请日：1995-02-24
申请人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
发明人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/76802 , H01L21/76829 , H01L21/7685 , H01L21/76877 , Y10S438/959
摘要： A conductive plug (46) is formed in a semiconductor device (30) by using an aluminum nitride glue layer (42). The glue layer is deposited on an interlayer dielectric (40) prior to forming a contact opening (44), such that the glue layer does not line the opening sidewalls or bottom. Tungsten or other plug material is then deposited in the opening and on the glue layer and subsequently polished or etched back to form the plug. The remaining portions of the glue layer may be left within the device or removed as deemed appropriate.
摘要翻译：通过使用氮化铝胶层（42）在半导体器件（30）中形成导电插塞（46）。在形成接触开口（44）之前，胶层沉积在层间电介质（40）上，使得胶层不与开口侧壁或底部对齐。然后将钨或其他塞子材料沉积在开口和胶层上，随后抛光或回蚀以形成塞子。胶层的剩余部分可以留在装置内或者视为适当的去除。

3. 发明授权

US5677231A Method for providing trench isolation 失效
标题翻译：提供沟槽隔离的方法
公开(公告)号：US5677231A
公开(公告)日：1997-10-14
申请号：US656817
申请日：1996-06-03
申请人： Papu D. Maniar , Robert W. Fiordalice
发明人： Papu D. Maniar , Robert W. Fiordalice
IPC分类号： H01L21/28 , H01L21/60 , H01L21/762 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/28 , H01L21/76224 , H01L21/76802 , Y10S148/02 , Y10S438/97
摘要： A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.
摘要翻译：制造沟槽隔离区域（32）以包括由氮化铝构成的沟槽衬垫（28）。氮化铝沟槽衬套可用于无边界接触应用中，其中在层间电介质（54）中蚀刻接触开口（56）并覆盖有源区域。（例如，掺杂区域52）和沟槽隔离区域。在使用对氮化铝有选择性的蚀刻化学形成开口期间，沟槽衬垫保护沟槽的拐角区域（58）处的P-N结以防止接合。通过保护接头，随后形成导电插塞（60）将不会使接头电短路，并将二极管泄漏保持在可接受的水平内。

4. 发明授权

US5652176A Method for providing trench isolation and borderless contact 失效
标题翻译：提供沟槽隔离和无边界接触的方法
公开(公告)号：US5652176A
公开(公告)日：1997-07-29
申请号：US393783
申请日：1995-02-24
申请人： Papu D. Maniar , Robert W. Fiordalice
发明人： Papu D. Maniar , Robert W. Fiordalice
IPC分类号： H01L21/28 , H01L21/60 , H01L21/762 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/28 , H01L21/76224 , H01L21/76802 , Y10S148/02 , Y10S438/97
摘要： A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.
摘要翻译：制造沟槽隔离区域（32）以包括由氮化铝构成的沟槽衬垫（28）。氮化铝沟槽衬垫可用于无边界接触应用中，其中在层间电介质（54）中蚀刻接触开口（56）并覆盖有源区域（例如，掺杂区域52）和沟槽隔离区域两者。在使用对氮化铝有选择性的蚀刻化学形成开口形成期间，沟槽衬垫保护沟槽的拐角区域（58）处的P-N结以防止接合。通过保护接头，随后形成导电插塞（60）将不会使接头电短路，并将二极管泄漏保持在可接受的水平内。

5. 发明授权

US5525542A Method for making a semiconductor device having anti-reflective coating 失效
标题翻译：制造具有抗反射涂层的半导体器件的方法
公开(公告)号：US5525542A
公开(公告)日：1996-06-11
申请号：US393781
申请日：1995-02-24
申请人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
发明人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
IPC分类号： G03F7/004 , G03F7/20 , H01L21/027 , H01L21/28
CPC分类号： H01L21/0276 , Y10S148/113 , Y10S438/952
摘要： An anti-reflective coating (ARC) (20) is formed over a reflective, conductive layer (18), such as polysilicon or aluminum, in a semiconductor device (10). The ARC is an aluminum nitride layer. During photolithography, the ARC absorbs radiation waves (30), particularly absorbing wavelengths under 300 nanometers, such as deep ultraviolet (DUV) radiation at 248 nanometers. Being absorbed by the ARC, the radiation waves are prevented from reflecting off the underlying conductive layer. Thus, resist mask (34) is patterned and developed true to the pattern on lithography mask (24), resulting in accurate replication into appropriate layers of the device.
摘要翻译：在半导体器件（10）中的反射导电层（18）（例如多晶硅或铝）上形成抗反射涂层（ARC）（20）。 ARC是氮化铝层。在光刻期间，ARC吸收辐射波（30），特别是吸收在300纳米以下的波长，例如248纳米的深紫外（DUV）辐射。被ARC吸收，辐射波被防止从下面的导电层反射出来。因此，抗蚀剂掩模（34）被图案化并且在光刻掩模（24）上的图案上真实地形成，导致准确地复制到器件的适当层中。

6. 发明授权

US06949457B1 Barrier enhancement 失效
标题翻译：障碍增强
公开(公告)号：US06949457B1
公开(公告)日：2005-09-27
申请号：US10761540
申请日：2004-01-21
申请人： Robert W. Fiordalice , Faivel Pintchovski
发明人： Robert W. Fiordalice , Faivel Pintchovski
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76865
摘要： A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.
摘要翻译：一种形成导电通孔的方法。形成第一导电层，在第一层上形成第二层。第二层具有期望的阻挡层性质。在第二层上形成第三非导电层。通孔穿过第三层被蚀刻，从而暴露通孔底部的第二层的一部分。通孔的底部的第二层的暴露部分重新分布，使得第二层的至少一部分从通孔的底部移除并沉积在通孔的侧壁的下部。在通孔内形成第四导电层以形成导电通孔。

7. 发明授权

US5783485A Process for fabricating a metallized interconnect 失效
标题翻译：用于制造金属化互连的工艺
公开(公告)号：US5783485A
公开(公告)日：1998-07-21
申请号：US684069
申请日：1996-07-19
申请人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
发明人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).
摘要翻译：金属化互连结构的制造方法包括形成覆盖铝层（34）的镶嵌互连（42）。嵌入式互连（42）形成在层间介质层内，该层间介质层被处理成包含位于互连通道（24）的底部的互连通道（24）和通孔开口（14）。选择性地沉积铝层（34）以至少部分地填充在互连通道（24）的底部处的通孔开口（14）。沉积粘附层（36）以覆盖通孔开口（14）内的铝层（34），并且第二铝层（38）被覆盖沉积并平坦化以在互连通道（...）中形成镶嵌互连（42） 24）。

8. 发明授权

US5391517A Process for forming copper interconnect structure 失效
标题翻译：形成铜互连结构的工艺
公开(公告)号：US5391517A
公开(公告)日：1995-02-21
申请号：US120097
申请日：1993-09-13
申请人： Avgerinos V. Gelatos , Robert W. Fiordalice
发明人： Avgerinos V. Gelatos , Robert W. Fiordalice
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L23/5226 , H01L21/32051 , H01L21/76838 , H01L23/53238 , H01L2924/0002
摘要： A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26). The titanium nitride layer (18) functions as a diffusion barrier preventing the diffusion of copper into the underlying dielectric layer (12), and the copper titanium intermetallic layer (26) provides an adhesive material, which adheres the copper layer (24) to the device substrate ( 10). Following the formation of the intermetallic layer (26), the device surface is planarized to form a planar surface (28), and to form an inlaid copper interconnect (30).
摘要翻译：提供了一种用于形成用纯铜金属制造的电互连的铜金属化结构和工艺。金属化结构包括介于介电层（12）中间的界面层（22）和铜互连（30）。界面层（22）用于将铜互连（30）粘附到器件衬底（10）并防止铜扩散到下面的介电层中。通过沉积第一钛层（16）然后顺序沉积氮化钛层（18）和第二钛层（20）来制造互连层（22）。沉积铜层（24）以覆盖第二钛层（20），并执行退火步骤以形成铜 - 钛金属间层（26）。氮化钛层（18）作为阻止铜扩散到下面的电介质层（12）中的扩散阻挡层而起作用，铜钛金属间化合物层（26）提供将铜层（24）粘合到器件衬底（10）。在形成金属间层（26）之后，将器件表面平坦化以形成平坦表面（28），并形成镶嵌铜互连（30）。

9. 发明授权

US5633199A Process for fabricating a metallized interconnect structure in a semiconductor device 失效
标题翻译：在半导体器件中制造金属化互连结构的工艺
公开(公告)号：US5633199A
公开(公告)日：1997-05-27
申请号：US556787
申请日：1995-11-02
申请人： Robert W. Fiordalice , Roc Blumenthal
发明人： Robert W. Fiordalice , Roc Blumenthal
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76877
摘要： A process for fabricating a metallized interconnect structure in a semiconductor device includes the steps of depositing a first aluminum layer (22) into a via opening (16) in a dielectric layer (18). A doping layer (24) is deposited by high density plasma sputtering to form a portion thereof in the bottom of the via opening (16). A second aluminum layer (26) is chemical vapor deposited to overlie the doping layer (24) and to fill the via opening (16). An annealing process can then be carried out to diffuse metal dopants from the doping layer (24) into nearby metal regions to provide a uniformly doped metal region within the via opening (16).
摘要翻译：在半导体器件中制造金属化互连结构的工艺包括以下步骤：将第一铝层（22）沉积在电介质层（18）中的通孔（16）中。通过高密度等离子体溅射沉积掺杂层（24）以在通孔开口（16）的底部形成其一部分。化学气相沉积以覆盖掺杂层（24）并填充通孔（16）的第二铝层（26）。然后可以执行退火工艺以将金属掺杂剂从掺杂层（24）扩散到附近的金属区域中，以在通孔开口（16）内提供均匀掺杂的金属区域。

10. 发明授权

US5358901A Process for forming an intermetallic layer 失效
标题翻译：用于形成金属间层的方法
公开(公告)号：US5358901A
公开(公告)日：1994-10-25
申请号：US24042
申请日：1993-03-01
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

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