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1. 发明授权

US5633199A Process for fabricating a metallized interconnect structure in a semiconductor device 失效
标题翻译：在半导体器件中制造金属化互连结构的工艺
公开(公告)号：US5633199A
公开(公告)日：1997-05-27
申请号：US556787
申请日：1995-11-02
申请人： Robert W. Fiordalice , Roc Blumenthal
发明人： Robert W. Fiordalice , Roc Blumenthal
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76877
摘要： A process for fabricating a metallized interconnect structure in a semiconductor device includes the steps of depositing a first aluminum layer (22) into a via opening (16) in a dielectric layer (18). A doping layer (24) is deposited by high density plasma sputtering to form a portion thereof in the bottom of the via opening (16). A second aluminum layer (26) is chemical vapor deposited to overlie the doping layer (24) and to fill the via opening (16). An annealing process can then be carried out to diffuse metal dopants from the doping layer (24) into nearby metal regions to provide a uniformly doped metal region within the via opening (16).
摘要翻译：在半导体器件中制造金属化互连结构的工艺包括以下步骤：将第一铝层（22）沉积在电介质层（18）中的通孔（16）中。通过高密度等离子体溅射沉积掺杂层（24）以在通孔开口（16）的底部形成其一部分。化学气相沉积以覆盖掺杂层（24）并填充通孔（16）的第二铝层（26）。然后可以执行退火工艺以将金属掺杂剂从掺杂层（24）扩散到附近的金属区域中，以在通孔开口（16）内提供均匀掺杂的金属区域。

2. 发明授权

US06949457B1 Barrier enhancement 失效
标题翻译：障碍增强
公开(公告)号：US06949457B1
公开(公告)日：2005-09-27
申请号：US10761540
申请日：2004-01-21
申请人： Robert W. Fiordalice , Faivel Pintchovski
发明人： Robert W. Fiordalice , Faivel Pintchovski
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76865
摘要： A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.
摘要翻译：一种形成导电通孔的方法。形成第一导电层，在第一层上形成第二层。第二层具有期望的阻挡层性质。在第二层上形成第三非导电层。通孔穿过第三层被蚀刻，从而暴露通孔底部的第二层的一部分。通孔的底部的第二层的暴露部分重新分布，使得第二层的至少一部分从通孔的底部移除并沉积在通孔的侧壁的下部。在通孔内形成第四导电层以形成导电通孔。

3. 发明授权

US5783485A Process for fabricating a metallized interconnect 失效
标题翻译：用于制造金属化互连的工艺
公开(公告)号：US5783485A
公开(公告)日：1998-07-21
申请号：US684069
申请日：1996-07-19
申请人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
发明人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).
摘要翻译：金属化互连结构的制造方法包括形成覆盖铝层（34）的镶嵌互连（42）。嵌入式互连（42）形成在层间介质层内，该层间介质层被处理成包含位于互连通道（24）的底部的互连通道（24）和通孔开口（14）。选择性地沉积铝层（34）以至少部分地填充在互连通道（24）的底部处的通孔开口（14）。沉积粘附层（36）以覆盖通孔开口（14）内的铝层（34），并且第二铝层（38）被覆盖沉积并平坦化以在互连通道（...）中形成镶嵌互连（42） 24）。

4. 发明授权

US5391517A Process for forming copper interconnect structure 失效
标题翻译：形成铜互连结构的工艺
公开(公告)号：US5391517A
公开(公告)日：1995-02-21
申请号：US120097
申请日：1993-09-13
申请人： Avgerinos V. Gelatos , Robert W. Fiordalice
发明人： Avgerinos V. Gelatos , Robert W. Fiordalice
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L23/5226 , H01L21/32051 , H01L21/76838 , H01L23/53238 , H01L2924/0002
摘要： A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26). The titanium nitride layer (18) functions as a diffusion barrier preventing the diffusion of copper into the underlying dielectric layer (12), and the copper titanium intermetallic layer (26) provides an adhesive material, which adheres the copper layer (24) to the device substrate ( 10). Following the formation of the intermetallic layer (26), the device surface is planarized to form a planar surface (28), and to form an inlaid copper interconnect (30).
摘要翻译：提供了一种用于形成用纯铜金属制造的电互连的铜金属化结构和工艺。金属化结构包括介于介电层（12）中间的界面层（22）和铜互连（30）。界面层（22）用于将铜互连（30）粘附到器件衬底（10）并防止铜扩散到下面的介电层中。通过沉积第一钛层（16）然后顺序沉积氮化钛层（18）和第二钛层（20）来制造互连层（22）。沉积铜层（24）以覆盖第二钛层（20），并执行退火步骤以形成铜 - 钛金属间层（26）。氮化钛层（18）作为阻止铜扩散到下面的电介质层（12）中的扩散阻挡层而起作用，铜钛金属间化合物层（26）提供将铜层（24）粘合到器件衬底（10）。在形成金属间层（26）之后，将器件表面平坦化以形成平坦表面（28），并形成镶嵌铜互连（30）。

5. 发明授权

US5358901A Process for forming an intermetallic layer 失效
标题翻译：用于形成金属间层的方法
公开(公告)号：US5358901A
公开(公告)日：1994-10-25
申请号：US24042
申请日：1993-03-01
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

6. 发明授权

US06218733B1 Semiconductor device having a titanium-aluminum compound 失效
标题翻译：具有钛 - 铝化合物的半导体器件
公开(公告)号：US06218733B1
公开(公告)日：2001-04-17
申请号：US08254854
申请日：1994-06-06
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

7. 发明授权

US06218302B1 Method for forming a semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US06218302B1
公开(公告)日：2001-04-17
申请号：US09121068
申请日：1998-07-21
申请人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
发明人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76882 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552 , H01L2924/013 , H01L2924/0105 , H01L2924/01026
摘要： An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
摘要翻译：互连（60）形成在衬底（10）上。在一个实施例中，将覆盖在衬底（10）上的粘合/阻挡层（81），铜合金晶种层（42）和铜膜（43）沉积，并且将衬底（10）退火。在替代实施例中，在衬底上沉积铜膜，并对铜膜进行退火。在另一个实施例中，在基板（10）上沉积粘合/阻挡层（81），种子层（82），导电膜（83）和铜合金封盖膜（84），以形成互连（92）。沉积和退火步骤可以在公共处理平台上进行。

8. 发明授权

US06187682B1 Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material 失效
标题翻译：惰性等离子体气体表面清洁过程是用物理气相沉积（PVD）进行的
公开(公告)号：US06187682B1
公开(公告)日：2001-02-13
申请号：US09084276
申请日：1998-05-26
申请人： Dean J. Denning , Rama I. Hegde , Sam S. Garcia , Robert W. Fiordalice
发明人： Dean J. Denning , Rama I. Hegde , Sam S. Garcia , Robert W. Fiordalice
IPC分类号： H01L21311
CPC分类号： H01L21/76843 , C23C14/022 , C23C14/358 , H01L21/02046 , H01L21/28518 , H01L21/2855 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/76804 , H01L21/76807 , H01L21/76814 , Y10S438/913
摘要： A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (26) into a chamber (12). A plasma (30) is generated within the chamber (12) using an inert, noble, or reducing gas. The gas is ionized to form ions (32) within the plasma (30). Power is provided to various components (16, 22, and 24) within the chamber (12) to ensure that the ions (32) are accelerated towards the wafer (26) during first stages of wafer processing. This acceleration of the ions (32) towards the wafer (26) will clean a surface of the wafer (26). Following this cleaning operation, power supplied within the chamber (12) is altered to accelerate the ions (32) into a reverse direction so that the ions (32) impact a sputter target (20). Due to ionic bombardment of the target (20), a material is sputtered onto a clean surface of the wafer (26) in an insitu manner.
摘要翻译：将物理溅射操作连同执行清洁操作的方法开始于将晶片（26）放入室（12）中。使用惰性，贵重或还原气体在室（12）内产生等离子体（30）。气体被离子化以在等离子体（30）内形成离子（32）。功率被提供到腔室（12）内的各种部件（16,22和24），以确保离子（32）在晶片处理的第一阶段期间朝向晶片（26）加速。离子（32）朝向晶片（26）的加速将清洁晶片（26）的表面。在该清洁操作之后，改变在室（12）内供应的功率以将离子（32）加速到相反方向，使得离子（32）撞击溅射靶（20）。由于靶（20）的离子轰击，材料以本体的方式溅射到晶片（26）的清洁表面上。

9. 发明授权

US5429989A Process for fabricating a metallization structure in a semiconductor device 失效
标题翻译：在半导体器件中制造金属化结构的工艺
公开(公告)号：US5429989A
公开(公告)日：1995-07-04
申请号：US190966
申请日：1994-02-03
申请人： Robert W. Fiordalice , Faivel S. Pintchovski
发明人： Robert W. Fiordalice , Faivel S. Pintchovski
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/28556 , H01L21/76843
摘要： A process for fabricating a metallization structure includes the formation of an interlayer (20) using an MOCVD deposition process. A metal-organic precursor, having as one component tungsten, is used to deposit the interlayer (20) onto a surface region (18) of a substrate (10) at the bottom of an opening (16). The MOCVD deposition process forms a conformal layer which evenly coats all surfaces of the opening (16). Next, a refractory metal layer (22) is deposited to overlie the interlayer (20). Because of conformal nature of the MOCVD deposition process, refractory metal layer can be formed using corrosive gasses such as tungsten hexafluoride.
摘要翻译：用于制造金属化结构的工艺包括使用MOCVD沉积工艺形成中间层（20）。使用具有钨一种组分的金属有机前体将中间层（20）沉积在开口（16）的底部的基板（10）的表面区域（18）上。 MOCVD沉积工艺形成均匀地涂覆开口（16）的所有表面的共形层。接下来，沉积难熔金属层（22）以覆盖中间层（20）。由于MOCVD沉积工艺的保形性，难熔金属层可以使用六氟化钨等腐蚀性气体形成。

10. 发明授权

US07446416B2 Barrier material formation in integrated circuit structures 有权
标题翻译：集成电路结构中的阻挡材料形成
公开(公告)号：US07446416B2
公开(公告)日：2008-11-04
申请号：US11137166
申请日：2005-05-25
申请人： Robert W. Fiordalice , Faivel Pintchovski
发明人： Robert W. Fiordalice , Faivel Pintchovski
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76865
摘要： A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.
摘要翻译：一种形成导电通孔的方法。形成第一导电层，在第一层上形成第二层。第二层具有期望的阻挡层性质。在第二层上形成第三非导电层。通孔穿过第三层被蚀刻，从而暴露通孔底部的第二层的一部分。通孔的底部的第二层的暴露部分重新分布，使得第二层的至少一部分从通孔的底部移除并沉积在通孔的侧壁的下部。在通孔内形成第四导电层以形成导电通孔。

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