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1. 发明授权

US5494523A Controlling plasma particulates by contouring the plasma sheath using materials of differing RF impedances 失效
标题翻译：通过使用不同RF阻抗的材料轮廓化等离子体护套来控制等离子体颗粒
公开(公告)号：US5494523A
公开(公告)日：1996-02-27
申请号：US393527
申请日：1995-02-23
申请人： Robert J. Steger , Charles S. Rhoades , Anand Gupta
发明人： Robert J. Steger , Charles S. Rhoades , Anand Gupta
IPC分类号： H01L21/02 , H01J37/32 , H01L21/00 , C23C1/00
CPC分类号： H01J37/32431
摘要： A plasma processing apparatus including a wafer supporting pedestal which is designed to reduce particle trapping phenomena. In a region of the pedestal surface which surrounds or abuts the wafer, the pedestal has a permittivity which is substantially equal to or greater than that of the wafer surface. As a result, the sheath boundary is reshaped to reduce particle trapping.
摘要翻译：一种等离子体处理装置，包括晶片支撑基座，其被设计成减少颗粒捕获现象。在围绕或邻接晶片的基座表面的区域中，基座具有基本上等于或大于晶片表面的介电常数的介电常数。结果，护套边界重新成形以减少颗粒捕获。

2. 发明授权

US5423918A Method for reducing particulate contamination during plasma processing of semiconductor devices 失效
标题翻译：减少半导体器件等离子体处理过程中颗粒污染的方法
公开(公告)号：US5423918A
公开(公告)日：1995-06-13
申请号：US124900
申请日：1993-09-21
申请人： Anand Gupta , Charles S. Rhoades , Yan Ye , Joseph Lanucha
发明人： Anand Gupta , Charles S. Rhoades , Yan Ye , Joseph Lanucha
IPC分类号： H01L21/302 , C23C16/44 , H01J37/32 , H01L21/306 , H01L21/3065 , H01L21/68 , H01L21/687 , B08B6/00
CPC分类号： H01L21/68721 , C23C16/4401 , H01J37/32834 , H01L21/02046 , H01L21/68 , H01J2237/022
摘要： A technique for removing particles from above a semiconductor wafer, particularly particles that are trapped in a plasma chamber during processing of the wafer. Trapped particles are usually not all drawn out with gases exhausted from the chamber, in part because a peripheral focus ring and clamping mechanism impede their flow. In the method of the invention, the focus ring and clamping mechanism are raised on completion of processing, but before radio-frequency (rf) power is disconnected from the process chamber. Trapped particles are then easily flowed from the chamber with an introduced inert gas, and the level of particulate contamination of the wafer is significantly reduced.
摘要翻译：一种用于从半导体晶片上方去除颗粒的技术，特别是在晶片加工期间被捕获在等离子体室中的颗粒。被捕获的颗粒通常不会被从室排出的气体全部抽出，部分是因为外围聚焦环和夹紧机构阻碍了它们的流动。在本发明的方法中，聚焦环和夹持机构在处理完成之后，但在射频（RF）功率与处理室断开之前升高。捕获的颗粒然后容易地从引入的惰性气体从室流出，并且晶片的颗粒污染物的水平显着降低。

3. 发明授权

US4920403A Selective tungsten interconnection for yield enhancement 失效
标题翻译：选择性钨互连以提高产量
公开(公告)号：US4920403A
公开(公告)日：1990-04-24
申请号：US338682
申请日：1989-04-17
申请人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
发明人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52
CPC分类号： H01L21/7684 , H01L21/76886
摘要： Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.4 at a rate between 3-10 standard cubic centimeters per minute, WF.sub.6 at a rate between 3-25 standard cubic centimeters per minute, and H.sub.2 at a rate between 25-100 standard cubic centimeters per minute. Then the exposed metal interconnection lines are processed at a pressure between 50-200 m Torr, a temperature between 250-350 degrees Celsius, and a deposition rate between 2000-10000 Angstroms per minute to form the fully interconnected metal lines. The present method improves the yields of multi-level metal integrated circuits and maximizes the potential gate usage therein. The conformal deposition of selective tungsten enhances the yields of integrated circuits and tungsten capping on aluminum metal lines, for example provides for a better electromigration resistance interconnection.
摘要翻译：在集成电路中制造金属互连线的方法。通常，一种方法包括以下步骤：在介电间氧化物层上沉积金属层。金属层被图案化和蚀刻以在氧化物层上形成金属互连线。选择性地将钨沉积到蚀刻层上以完全形成金属互连线。另外，在第二种方法中，钨层可以在金属层之前沉积。这形成完全封装在钨中的金属线。此外，在制造的集成电路中用于修复断裂的金属线路的选择性钨。使用化学气相沉积工艺沉积选择性钨，并沉积到形成在集成电路中的被掩蔽和蚀刻的第二层（或更高）金属线上。选择性沉积钨的方法包括以3到10标准立方厘米/分钟的速率将金属互连线暴露于SiH 4的混合物，以3-25标准立方厘米/分钟的速率暴露于金属互连线和H2 一个25-100标准立方厘米每分钟的速率。然后暴露的金属互连线在50-200m乇，250-350摄氏度的温度和2000-10000埃每分钟的沉积速率之间的压力下进行处理，以形成完全互连的金属线。本方法提高了多级金属集成电路的产量，并使其中的栅极使用最大化。选择性钨的共形沉积增强了集成电路的产量和铝金属线上的钨封盖，例如提供了更好的电迁移电阻互连。

4. 发明授权

US5387556A Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub. 2 失效
标题翻译：使用HC1，含Cl的蚀刻剂和N 2蚀刻铝及其合金
公开(公告)号：US5387556A
公开(公告)日：1995-02-07
申请号：US21831
申请日：1993-02-24
申请人： Diana M. Xiaobing , Charles S. Rhoades
发明人： Diana M. Xiaobing , Charles S. Rhoades
IPC分类号： H01L21/302 , C23F4/00 , H01L21/3065 , H01L21/3213 , H01L21/283
CPC分类号： C23F4/00 , H01L21/32136
摘要： A process for etching aluminum from a substrate, where portions of the aluminum are protected by a resist material, is described. The substrate is placed into a chamber and a process gas comprising HCl, Cl-containing etchant and N.sub.2 is introduced in the chamber. A plasma is generated in the chamber to generate from the process gas an etch gas that etches aluminum from the substrate at fast rates, with good selectivity, reduced profile microloading, and substantially only anisotropic etching.
摘要翻译：描述了从基板上蚀刻铝的方法，其中部分铝被抗蚀剂材料保护。将衬底放置在室中，并且将包含HCl，含Cl的蚀刻剂和N 2的工艺气体引入室中。在室中产生等离子体，以从处理气体中产生蚀刻气体，该蚀刻气体以快速速率从基板蚀刻铝，具有良好的选择性，减小的轮廓微载荷，并且基本上仅进行各向异性蚀刻。

5. 发明授权

US5384009A Plasma etching using xenon 失效
标题翻译：使用氙气等离子体蚀刻
公开(公告)号：US5384009A
公开(公告)日：1995-01-24
申请号：US78131
申请日：1993-06-16
申请人： Steven Mak , Brian Shieh , Charles S. Rhoades
发明人： Steven Mak , Brian Shieh , Charles S. Rhoades
IPC分类号： H01L21/302 , C23F4/00 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32136 , C23F4/00
摘要： A process for selectively etching a substrate, having grain boundaries and a resist material thereon, is described. The substrate is placed into an etch zone and a process gas comprising a primary etchant, a secondary etchant, and xenon is introduced into the etch zone. A plasma is generated in the zone to form an etch gas from the process gas, that substantially anisotropically etches the substrate at fast rates, with good selectivity, and reduced profile microloading. Preferably the primary etchant comprises Cl.sub.2, and the secondary etchant comprises BCl.sub.3.
摘要翻译：描述了一种用于选择性地蚀刻其上具有晶界和其上的抗蚀剂材料的衬底的工艺。将衬底放置在蚀刻区中，并且将包含初级蚀刻剂，二次蚀刻剂和氙的工艺气体引入蚀刻区。在该区域中产生等离子体以形成来自工艺气体的蚀刻气体，基本上各向异性地以快速的速率蚀刻衬底，具有良好的选择性和减少的轮廓微载物。优选地，初级蚀刻剂包括Cl 2，二级蚀刻剂包括BCl 3。

6. 发明授权

US4961822A Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten 失效
标题翻译：具有钛钨和选择性CVD钨的完全凹陷互连方案
公开(公告)号：US4961822A
公开(公告)日：1990-10-09
申请号：US338681
申请日：1989-04-17
申请人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
发明人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/32051 , Y10S257/90
摘要： A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer. Subsequent metal levels may be fabricated by repeating the method starting with the steps of depositing the oxide over the formed higher-order metal lines and forming the metal plugs in the oxide layer.
摘要翻译：一种在多级金属半导体器件中制造高阶金属互连层的方法。半导体器件具有至少一个金属层，设置在金属层上的氧化物层和设置在连接到金属层的氧化物层中的金属插塞。在氧化物层上形成反向光刻胶掩模，该掩模蚀刻以形成限定高级金属层的沟槽。包含钛钨或铝的粘合层沉积在与金属塞接触的光致抗蚀剂掩模的顶部上。然后将低粘度的光致抗蚀剂层沉积在粘附层的顶部。然后对粘合层和低粘度的光致抗蚀剂层进行各向异性蚀刻，然后除去低粘度的光致抗蚀剂层以暴露粘附层。最后，诸如钨或钼的选择性金属例如沉积在沟槽中的粘附层的顶部上以形成高级金属互连层。随后的金属水平可以通过以下步骤制造：从在所形成的高级金属线上沉积氧化物并在氧化物层中形成金属塞的步骤开始。

7. 发明授权

US5486235A Plasma dry cleaning of semiconductor processing chambers 失效
标题翻译：半导体处理室的等离子体干洗
公开(公告)号：US5486235A
公开(公告)日：1996-01-23
申请号：US104318
申请日：1993-08-09
申请人： Yan Ye , Charles S. Rhoades , Gerald Z. Yin
发明人： Yan Ye , Charles S. Rhoades , Gerald Z. Yin
IPC分类号： C23C14/00 , B08B7/00 , C23C16/44 , H01L21/00 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065
CPC分类号： H01L21/02046 , B08B7/0035 , C23C16/4405 , H01L21/67028 , H01L21/67034 , Y10S438/905
摘要： The plasma dry cleaning rate of semiconductor process chamber walls can be improved by placing a non-gaseous dry cleaning enhancement material in the position which was occupied by the workpiece during semiconductor processing. The non-gaseous dry cleaning enhancement material is either capable of generating dry cleaning reactive species and/or of reducing the consumption of the dry cleaning reactive species generated from the plasma gas feed to the process chamber.When process chamber non-volatile contaminant deposits are removed from plasma process chamber surfaces during plasma dry cleaning by placing a non-gaseous source of reactive-species-generating material within the plasma process chamber, the non-gaseous source of reactive-species-generating material need not be located upon or adjacent the workpiece support platform: however, this location provides excellent cleaning results in typical process chamber designs.
摘要翻译：通过在半导体处理期间将非气态干洗增强材料置于被工件占据的位置，可以改善半导体处理室壁的等离子体干洗率。非气态干洗增强材料能够产生干洗反应物质和/或降低从等离子体气体进料到处理室产生的干洗反应物质的消耗。当在等离子体干洗期间通过将等离子体处理室内的非气态反应性物质产生材料源放置在等离子体处理室表面中来处理室非挥发性污染物沉积物时，产生非反应性物质的非气态源材料不必位于工件支撑平台上或邻近工件支撑平台：然而，该位置在典型的工艺室设计中提供了极好的清洁效果。

8. 发明授权

US5545289A Passivating, stripping and corrosion inhibition of semiconductor substrates 失效
标题翻译：半导体衬底的钝化，剥离和腐蚀抑制
公开(公告)号：US5545289A
公开(公告)日：1996-08-13
申请号：US268377
申请日：1994-06-29
申请人： Jian Chen , James S. Papanu , Steve S. Y. Mak , Carmel Ish-Shalom , Peter Hsieh , Wesley G. Lau , Charles S. Rhoades , Brian Shieh , Ian S. Latchford , Karen A. Williams , Victoria Yu-Wang
发明人： Jian Chen , James S. Papanu , Steve S. Y. Mak , Carmel Ish-Shalom , Peter Hsieh , Wesley G. Lau , Charles S. Rhoades , Brian Shieh , Ian S. Latchford , Karen A. Williams , Victoria Yu-Wang
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/02071 , H01L21/31138 , Y10S438/958
摘要： A process for passivating, and optionally stripping and inhibiting corrosion of an etched substrate (20), is described. In the process, a substrate (20) having etchant byproducts (24) thereon, is placed into a vacuum chamber (52), and passivated in a multicycle passivation process comprising at least two passivating steps. In each passivating step, passivating gas is introduced into the vacuum chamber (52) and a plasma is generated from the passivating gas. When the substrate also has remnant resist (26) thereon, the resist (26) is stripped in a multicycle passivation and stripping process, each cycle including a passivating step and a stripping step. The stripping step is performed by introducing a stripping gas into the vacuum chamber (52) and generating a plasma from the stripping gas. In the multicycle process, the passivating and optional stripping steps, are repeated at least once in the same order that the steps were done. Alternatively, the substrate (20) can also be passivated in a single cycle process using a passivating gas comprising water vapor, oxygen, and nitrogen. Optionally, corrosion of the substrate is further inhibited by introducing an amine vapor into the vacuum chamber (52) so that amine adsorps onto the substrate (20), forming a corrosion inhibition amine layer on the surface of the substrate (20).
摘要翻译：描述了钝化和任选地剥离和抑制腐蚀的衬底（20）的腐蚀的方法。在该方法中，将具有蚀刻剂副产物（24）的衬底（20）放置在真空室（52）中，并且在包括至少两个钝化步骤的多圈钝化工艺中钝化。在每个钝化步骤中，将钝化气体引入真空室（52）中，并从钝化气体产生等离子体。当衬底上还具有残余抗蚀剂（26）时，抗蚀剂（26）在多周期钝化和剥离过程中被剥离，每个循环包括钝化步骤和剥离步骤。通过将汽提气体引入真空室（52）并从汽提气体产生等离子体来进行汽提步骤。在多周期过程中，钝化和可选的剥离步骤以与步骤相同的顺序重复至少一次。或者，也可以使用包括水蒸气，氧气和氮气的钝化气体在单周期过程中钝化基板（20）。任选地，通过将胺蒸气引入真空室（52）进一步抑制基板的腐蚀，使得胺吸附到基板（20）上，在基板（20）的表面上形成腐蚀抑制胺层。

9. 发明授权

US5221424A Method for removal of photoresist over metal which also removes or inactivates corosion-forming materials remaining from previous metal etch 失效
标题翻译：去除金属上的光致抗蚀剂的方法，其也去除或钝化从先前金属蚀刻残留的形成腐蚀性材料
公开(公告)号：US5221424A
公开(公告)日：1993-06-22
申请号：US796096
申请日：1991-11-21
申请人： Charles S. Rhoades
发明人： Charles S. Rhoades
IPC分类号： G03F7/42 , H01L21/02 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/02071 , G03F7/427 , H01L21/31138
摘要： A process is described for removing from an integrated circuit structure photoresist remaining after a metal etch which also removes or inactivates a sufficient amount of any remaining chlorine residues remaining from the previous metal etch to inhibit corrosion of the remaining metal for at least 24 hours. The process includes a first stripping step associated with a plasma, using either O.sub.2 gas and one or more fluorocarbon gases, or O.sub.2 gas and N.sub.2 gas; followed by a subsequent step using a combination of H.sub.2 O.sub.2 /H.sub.2 O vapors, O.sub.2 gas, and optionally N.sub.2 gas associated with a plasma. Preferably, the plasma is generated in a microwave plasma generator located upstream of the stripping chamber, and the stripping gases pass through this generator so that reactive species produced from the gases in the plasma enter the stripping chamber.
摘要翻译：描述了从金属蚀刻后残留的集成电路结构光刻胶中去除的过程，其还去除或消除了从先前的金属蚀刻残留的足够量的剩余氯残余物以抑制剩余金属的腐蚀至少24小时。该方法包括使用O 2气体和一种或多种碳氟化合物气体或O 2气体和N 2气体与等离子体相关联的第一汽提步骤; 随后是使用与等离子体相关联的H 2 O 2 / H 2 O蒸气，O 2气体和任选的N 2气的组合的随后步骤。优选地，在位于汽提室上游的微波等离子体发生器中产生等离子体，并且汽提气体通过该发生器，使得从等离子体中产生的反应物质进入汽提室。

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