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1. 发明授权

US4920403A Selective tungsten interconnection for yield enhancement 失效
标题翻译：选择性钨互连以提高产量
公开(公告)号：US4920403A
公开(公告)日：1990-04-24
申请号：US338682
申请日：1989-04-17
申请人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
发明人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52
CPC分类号： H01L21/7684 , H01L21/76886
摘要： Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.4 at a rate between 3-10 standard cubic centimeters per minute, WF.sub.6 at a rate between 3-25 standard cubic centimeters per minute, and H.sub.2 at a rate between 25-100 standard cubic centimeters per minute. Then the exposed metal interconnection lines are processed at a pressure between 50-200 m Torr, a temperature between 250-350 degrees Celsius, and a deposition rate between 2000-10000 Angstroms per minute to form the fully interconnected metal lines. The present method improves the yields of multi-level metal integrated circuits and maximizes the potential gate usage therein. The conformal deposition of selective tungsten enhances the yields of integrated circuits and tungsten capping on aluminum metal lines, for example provides for a better electromigration resistance interconnection.
摘要翻译：在集成电路中制造金属互连线的方法。通常，一种方法包括以下步骤：在介电间氧化物层上沉积金属层。金属层被图案化和蚀刻以在氧化物层上形成金属互连线。选择性地将钨沉积到蚀刻层上以完全形成金属互连线。另外，在第二种方法中，钨层可以在金属层之前沉积。这形成完全封装在钨中的金属线。此外，在制造的集成电路中用于修复断裂的金属线路的选择性钨。使用化学气相沉积工艺沉积选择性钨，并沉积到形成在集成电路中的被掩蔽和蚀刻的第二层（或更高）金属线上。选择性沉积钨的方法包括以3到10标准立方厘米/分钟的速率将金属互连线暴露于SiH 4的混合物，以3-25标准立方厘米/分钟的速率暴露于金属互连线和H2 一个25-100标准立方厘米每分钟的速率。然后暴露的金属互连线在50-200m乇，250-350摄氏度的温度和2000-10000埃每分钟的沉积速率之间的压力下进行处理，以形成完全互连的金属线。本方法提高了多级金属集成电路的产量，并使其中的栅极使用最大化。选择性钨的共形沉积增强了集成电路的产量和铝金属线上的钨封盖，例如提供了更好的电迁移电阻互连。

2. 发明授权

US4961822A Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten 失效
标题翻译：具有钛钨和选择性CVD钨的完全凹陷互连方案
公开(公告)号：US4961822A
公开(公告)日：1990-10-09
申请号：US338681
申请日：1989-04-17
申请人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
发明人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/32051 , Y10S257/90
摘要： A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer. Subsequent metal levels may be fabricated by repeating the method starting with the steps of depositing the oxide over the formed higher-order metal lines and forming the metal plugs in the oxide layer.
摘要翻译：一种在多级金属半导体器件中制造高阶金属互连层的方法。半导体器件具有至少一个金属层，设置在金属层上的氧化物层和设置在连接到金属层的氧化物层中的金属插塞。在氧化物层上形成反向光刻胶掩模，该掩模蚀刻以形成限定高级金属层的沟槽。包含钛钨或铝的粘合层沉积在与金属塞接触的光致抗蚀剂掩模的顶部上。然后将低粘度的光致抗蚀剂层沉积在粘附层的顶部。然后对粘合层和低粘度的光致抗蚀剂层进行各向异性蚀刻，然后除去低粘度的光致抗蚀剂层以暴露粘附层。最后，诸如钨或钼的选择性金属例如沉积在沟槽中的粘附层的顶部上以形成高级金属互连层。随后的金属水平可以通过以下步骤制造：从在所形成的高级金属线上沉积氧化物并在氧化物层中形成金属塞的步骤开始。

3. 发明授权

US5260227A Method of making a self aligned static induction transistor 失效
标题翻译：制造自对准静电感应晶体管的方法
公开(公告)号：US5260227A
公开(公告)日：1993-11-09
申请号：US981032
申请日：1992-11-24
申请人： Joseph E. Farb , Kuan Y. Liao , Maw-Rong Chin
发明人： Joseph E. Farb , Kuan Y. Liao , Maw-Rong Chin
IPC分类号： H01L29/80 , H01L21/335 , H01L21/265
CPC分类号： H01L29/66416
摘要： A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.

4. 发明授权

US4847111A Plasma-nitridated self-aligned tungsten system for VLSI interconnections 失效
标题翻译：用于VLSI互连的等离子氮化自对准钨系统
公开(公告)号：US4847111A
公开(公告)日：1989-07-11
申请号：US213861
申请日：1988-06-30
申请人： Yu C. Chow , Kuan-Yang Liao , Maw-Rong Chin
发明人： Yu C. Chow , Kuan-Yang Liao , Maw-Rong Chin
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L23/52
CPC分类号： H01L29/66575 , H01L21/28518 , H01L29/41783
摘要： A process for forming a diffusion barrier on exposed silicon and polysilicon contacts of an integrated circuit including the step of chemically vapor depositing a layer of tungsten in a self-aligned manner on the exposed contact areas. The layer of tungsten is plasma nitridated to form a tungsten nitride layer and to partially form a tungsten silicide layer adjacent the contact areas. The formation of the tungsten silicide layer is completed by thermal annealing.
摘要翻译：一种用于在集成电路的暴露的硅和多晶硅触点上形成扩散阻挡层的工艺，包括以自对准方式在暴露的接触区域上化学气相沉积钨层的步骤。钨层被等离子体氮化以形成氮化钨层，并部分地形成邻近接触区域的硅化钨层。通过热退火完成硅化钨层的形成。

5. 发明授权

US5140390A High speed silicon-on-insulator device 失效
标题翻译：高速绝缘体上硅器件
公开(公告)号：US5140390A
公开(公告)日：1992-08-18
申请号：US646119
申请日：1991-01-28
申请人： Mei Li , Chen-Chi P. Chang , Maw-Rong Chin
发明人： Mei Li , Chen-Chi P. Chang , Maw-Rong Chin
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L27/12
CPC分类号： H01L29/66772 , H01L21/76243 , H01L21/76264 , H01L21/8238 , H01L27/092 , H01L27/1203 , H01L21/76267 , H01L21/76283
摘要： High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films. The present invention is fabricated using present equipment and available technology, and provides an easy, straight forward and cost-effective process to fabricate very high speed CMOS devices which are latch-up free and radiation hardened.
摘要翻译：高速绝缘体上的辐射硬化半导体器件及其制造方法。从在掩埋氧化物层（11）上具有硅层（12）的SIMOX晶片（10）开始，P阱和N阱掩模与过大的多晶硅掩模（16）对准。这产生相对较厚的源极和漏极区域（18）和相对薄的栅极区域（17）。相对较厚的源极和漏极区域（18）降低了干接触蚀刻问题的风险。在形成有源区域之前调整N沟道和P沟道阈值电压，从而基本上消除边沿和反向沟道泄漏。牺牲薄氧化物层（21）用于制造N阱和P阱注入，以便控制前和后通道阈值电压调节。获得良好的掺杂特性控制，导致极好的阈值电压控制和较低的边缘和背面通道泄漏。使用本发明的方法制造的器件的速度由于较薄的绝缘体上硅膜导致的电容降低而高。本发明使用本设备和可用技术制造，并且提供了一种容易，直接的和具有成本效益的工艺，以制造无闩锁和辐射硬化的非常高速的CMOS器件。

6. 发明授权

US5479047A Self-aligned bipolar transistor with very thin dielectric layer interfacing between poly and active area 失效
标题翻译：自对准双极晶体管，具有非常薄的电介质层，在聚和有源区域之间进行接口
公开(公告)号：US5479047A
公开(公告)日：1995-12-26
申请号：US42172
申请日：1993-04-02
申请人： Kuan-Yang Liao , Maw-Rong Chin
发明人： Kuan-Yang Liao , Maw-Rong Chin
IPC分类号： H01L21/225 , H01L21/331 , H01L29/732 , H01L29/73 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/2256 , H01L29/7322
摘要： A modification of the self-aligned double poly fabrication process for bipolar transistors employs a thin sacrificial dielectric film to protect the wafer surface during the etching of an emitter opening through an overlying polysilicon contact layer. The sacrificial layer, which is preferably silicon dioxide for a silicon wafer, is thick enough to serve as an etch stop but thin enough to permit dopant from the polysilicon contact to be driven-in through the film to form an extrinsic base region. The dielectric film is left in place under the base contact polysilicon, but removed from the emitter area. It is preferably about 10-20 Angstroms thick when implemented as a silicon dioxide film. With this material system, the extrinsic base drive-in is preferably performed either by a rapid isothermal anneal at about 1,000.degree. C. for about 30-40 seconds, or in a furnace at about 975.degree. C. for about 10 minutes.
摘要翻译：双极晶体管的自对准双重多晶硅制造工艺的修改采用薄牺牲电介质膜，以在通过覆盖多晶硅接触层蚀刻发射极开口期间保护晶片表面。牺牲层（其优选用于硅晶片的二氧化硅）足够厚以用作蚀刻停止层，但足够薄以允许来自多晶硅接触件的掺杂剂通过膜被驱入以形成外部基极区域。电介质膜留在基底接触多晶硅下方，但从发射极区域移除。当实施为二氧化硅膜时，优选为约10-20埃厚。对于该材料系统，外部基极驱入优选通过在约1000℃下快速等温退火约30-40秒或在约975℃的炉中进行约10分钟。

7. 发明授权

US5389575A Self-aligned contact diffusion barrier method 失效
标题翻译：自对准接触扩散阻挡法
公开(公告)号：US5389575A
公开(公告)日：1995-02-14
申请号：US39718
申请日：1993-03-29
申请人： Maw-Rong Chin , Gary Warren , Kuan-Yang Liao
发明人： Maw-Rong Chin , Gary Warren , Kuan-Yang Liao
IPC分类号： H01L21/285 , H01L21/441
CPC分类号： H01L21/28568 , Y10S438/913
摘要： A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.
摘要翻译：在薄几何形状集成电路器件中形成接触扩散阻挡层的方法包括将第二材料注入覆盖在期望接触的半导体的低电阻率材料中。选择低电阻率和植入材料以彼此相互接触并形成接触扩散阻挡层。两种材料可以包括过渡金属，在这种情况下，扩散阻挡层是复合过渡金属。或者，低电阻率材料可以包括过渡金属，而用氮气进行注入。通过等离子体蚀刻，优选采用主动冷却来进行注入，其可以在与接触开口的蚀刻连续的步骤中组合。所产生的接触扩散阻挡层与接触开口自对准，仅在开口附近建立。

8. 发明授权

US5523244A Transistor fabrication method using dielectric protection layers to eliminate emitter defects 失效
标题翻译：使用介质保护层消除发射极缺陷的晶体管制造方法
公开(公告)号：US5523244A
公开(公告)日：1996-06-04
申请号：US359102
申请日：1994-12-19
申请人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
发明人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
IPC分类号： H01L21/331 , H01L29/423 , H01L21/265 , H01L49/00
CPC分类号： H01L29/66272 , H01L29/42304 , Y10S148/01 , Y10S148/124
摘要： A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.
摘要翻译：一种用于制造超自对准双极结型晶体管的方法，其通过在所有可能有害的蚀刻步骤期间提供非临界厚的电介质蚀刻停止（保护）层（116）来减少或消除在临界蚀刻步骤期间引起的发射极缺陷。在潜在有害的蚀刻步骤期间，例如用于形成关键器件结构的干式蚀刻工艺（例如发射极开口124），在半导体表面（110）的发射极区域（152）的上方提供氧化物或其它电介质层（116,130）使用诸如湿式蚀刻的非破坏性蚀刻方法来去除介电保护层（116,130）以形成不太关键的器件结构，和/或形成中间层开口，而不会损坏发射极中的硅表面（152）或其他关键区域。电介质蚀刻停止（保护）层（116,130）在形成发射极（152）和基极区域（142）之前通过湿式蚀刻而非临界厚并且通过湿蚀刻完全从器件的非本征基极区域（142） 144）。该方法导致更均匀，更低电阻基极连接，更高的芯片产量，更均匀的器件性能和更大的器件可靠性。

9. 发明授权

US5185535A Control of backgate bias for low power high speed CMOS/SOI devices 失效
标题翻译：控制低功率高速CMOS / SOI器件的背栅偏置
公开(公告)号：US5185535A
公开(公告)日：1993-02-09
申请号：US716151
申请日：1991-06-17
申请人： Joseph E. Farb , Mei Li , Chen-Chi P. Chang , Maw-Rong Chin
发明人： Joseph E. Farb , Mei Li , Chen-Chi P. Chang , Maw-Rong Chin
IPC分类号： H01L21/74 , H01L21/84 , H01L27/12
CPC分类号： H01L27/12 , H01L21/743 , H01L21/84 , Y10S257/901
摘要： Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.
摘要翻译：制造在绝缘体上硅衬底上的免费金属氧化物硅晶体管被配置为允许在相同衬底上的相邻互补器件的单独可控和独立的背栅极偏置。通过深度注入硼，背桥偏压P阱（26,126）位于N衬底前面的N衬底（17,117）上，该衬底位于互补对的N沟道晶体管的后面。背板偏置P阱（26,126）在器件的前部设置有电接触（48,148），如同N沟道硅衬底一样，可独立施加不同极性和适当大小的单独偏置电压。

10. 发明授权

US5686330A Method of making a self-aligned static induction transistor 失效
标题翻译：制造自对准静电感应晶体管的方法
公开(公告)号：US5686330A
公开(公告)日：1997-11-11
申请号：US716957
申请日：1996-09-23
申请人： Joseph E. Farb , Maw-Rong Chin
发明人： Joseph E. Farb , Maw-Rong Chin
IPC分类号： H01L21/76 , H01L21/335 , H01L29/772 , H01L29/80 , H01L21/265
CPC分类号： H01L29/66416 , H01L29/7722
摘要： A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions. This portion of the method comprises the steps of forming maskless self-aligned gate metallization, forming maskless self-aligned contacts to the gate metallization and filling the trench, forming source metallization, and forming a drain contact on the substrate. The method employs a single minimum geometry trench mask. The key features of the transistors are defined by the trench mask and related processing parameters. Because of the self-alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded gate junction.
摘要翻译：公开了制造自对准静电感应晶体管的方法。该方法包括制造具有有效面积的硅衬底。在活动区域周围形成保护环。形成源极和栅极区，并且在栅极区上形成根据本发明的自对准的相对较深的沟槽。这通过形成氧化物层并在氧化物层上形成多晶硅层来实现。第二氧化物层形成在多晶硅层上，然后被自对准掩模掩蔽。使用自对准掩模将沟槽蚀刻到源极和栅极区域中，并且在沟槽的底部形成栅极区域。然后通过形成栅极，源极和漏极区域来处理晶体管以完成。该方法的该部分包括以下步骤：形成无掩模自对准栅极金属化，在栅极金属化处形成无掩模自对准接触并填充沟槽，形成源极金属化，并在衬底上形成漏极接触。该方法采用单个最小几何沟槽掩模。晶体管的关键特征由沟槽掩模和相关的处理参数来定义。由于通过本发明实现的自对准，每单位面积的通道数量较多，这导致更高的跨导。此外，通过本发明消除了一些寄生电容，导致更快的操作速度。可变侧壁沟槽氧化物厚度允许根据所选择的厚度和更梯度的栅极结制造具有更高或更低击穿电压的静态感应晶体管。

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