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1. 发明授权

US4961822A Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten 失效
标题翻译：具有钛钨和选择性CVD钨的完全凹陷互连方案
公开(公告)号：US4961822A
公开(公告)日：1990-10-09
申请号：US338681
申请日：1989-04-17
申请人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
发明人： Kuan Y. Liao , Yu C. Chow , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/32051 , Y10S257/90
摘要： A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer. Subsequent metal levels may be fabricated by repeating the method starting with the steps of depositing the oxide over the formed higher-order metal lines and forming the metal plugs in the oxide layer.
摘要翻译：一种在多级金属半导体器件中制造高阶金属互连层的方法。半导体器件具有至少一个金属层，设置在金属层上的氧化物层和设置在连接到金属层的氧化物层中的金属插塞。在氧化物层上形成反向光刻胶掩模，该掩模蚀刻以形成限定高级金属层的沟槽。包含钛钨或铝的粘合层沉积在与金属塞接触的光致抗蚀剂掩模的顶部上。然后将低粘度的光致抗蚀剂层沉积在粘附层的顶部。然后对粘合层和低粘度的光致抗蚀剂层进行各向异性蚀刻，然后除去低粘度的光致抗蚀剂层以暴露粘附层。最后，诸如钨或钼的选择性金属例如沉积在沟槽中的粘附层的顶部上以形成高级金属互连层。随后的金属水平可以通过以下步骤制造：从在所形成的高级金属线上沉积氧化物并在氧化物层中形成金属塞的步骤开始。

2. 发明授权

US4920403A Selective tungsten interconnection for yield enhancement 失效
标题翻译：选择性钨互连以提高产量
公开(公告)号：US4920403A
公开(公告)日：1990-04-24
申请号：US338682
申请日：1989-04-17
申请人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
发明人： Yu C. Chow , Kuan Y. Liao , Maw-Rong Chin , Charles S. Rhoades
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52
CPC分类号： H01L21/7684 , H01L21/76886
摘要： Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.4 at a rate between 3-10 standard cubic centimeters per minute, WF.sub.6 at a rate between 3-25 standard cubic centimeters per minute, and H.sub.2 at a rate between 25-100 standard cubic centimeters per minute. Then the exposed metal interconnection lines are processed at a pressure between 50-200 m Torr, a temperature between 250-350 degrees Celsius, and a deposition rate between 2000-10000 Angstroms per minute to form the fully interconnected metal lines. The present method improves the yields of multi-level metal integrated circuits and maximizes the potential gate usage therein. The conformal deposition of selective tungsten enhances the yields of integrated circuits and tungsten capping on aluminum metal lines, for example provides for a better electromigration resistance interconnection.
摘要翻译：在集成电路中制造金属互连线的方法。通常，一种方法包括以下步骤：在介电间氧化物层上沉积金属层。金属层被图案化和蚀刻以在氧化物层上形成金属互连线。选择性地将钨沉积到蚀刻层上以完全形成金属互连线。另外，在第二种方法中，钨层可以在金属层之前沉积。这形成完全封装在钨中的金属线。此外，在制造的集成电路中用于修复断裂的金属线路的选择性钨。使用化学气相沉积工艺沉积选择性钨，并沉积到形成在集成电路中的被掩蔽和蚀刻的第二层（或更高）金属线上。选择性沉积钨的方法包括以3到10标准立方厘米/分钟的速率将金属互连线暴露于SiH 4的混合物，以3-25标准立方厘米/分钟的速率暴露于金属互连线和H2 一个25-100标准立方厘米每分钟的速率。然后暴露的金属互连线在50-200m乇，250-350摄氏度的温度和2000-10000埃每分钟的沉积速率之间的压力下进行处理，以形成完全互连的金属线。本方法提高了多级金属集成电路的产量，并使其中的栅极使用最大化。选择性钨的共形沉积增强了集成电路的产量和铝金属线上的钨封盖，例如提供了更好的电迁移电阻互连。

3. 发明授权

US4847111A Plasma-nitridated self-aligned tungsten system for VLSI interconnections 失效
标题翻译：用于VLSI互连的等离子氮化自对准钨系统
公开(公告)号：US4847111A
公开(公告)日：1989-07-11
申请号：US213861
申请日：1988-06-30
申请人： Yu C. Chow , Kuan-Yang Liao , Maw-Rong Chin
发明人： Yu C. Chow , Kuan-Yang Liao , Maw-Rong Chin
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L23/52
CPC分类号： H01L29/66575 , H01L21/28518 , H01L29/41783
摘要： A process for forming a diffusion barrier on exposed silicon and polysilicon contacts of an integrated circuit including the step of chemically vapor depositing a layer of tungsten in a self-aligned manner on the exposed contact areas. The layer of tungsten is plasma nitridated to form a tungsten nitride layer and to partially form a tungsten silicide layer adjacent the contact areas. The formation of the tungsten silicide layer is completed by thermal annealing.
摘要翻译：一种用于在集成电路的暴露的硅和多晶硅触点上形成扩散阻挡层的工艺，包括以自对准方式在暴露的接触区域上化学气相沉积钨层的步骤。钨层被等离子体氮化以形成氮化钨层，并部分地形成邻近接触区域的硅化钨层。通过热退火完成硅化钨层的形成。

4. 发明授权

US4737474A Silicide to silicon bonding process 失效
标题翻译：硅化物与硅键合工艺
公开(公告)号：US4737474A
公开(公告)日：1988-04-12
申请号：US931479
申请日：1986-11-17
申请人： J. B. Price , Yu C. Chow , John Mendonca , Schyi-Yi Wu
发明人： J. B. Price , Yu C. Chow , John Mendonca , Schyi-Yi Wu
IPC分类号： H01L21/3205 , H01L21/28 , H01L23/52 , H01L29/78
CPC分类号： H01L21/28026 , H01L21/28061 , Y10S148/147
摘要： A process for forming a bonding layer comprising amorphous silicon, titanium, chromium, or tungsten, between the silicide and the N+ polysilicon layer is disclosed. The bonding layer is preferably less than 50 nm. thick. After the bonding layer is deposited, a silicide layer is deposited and the wafer is then sintered at 900.degree.-1000.degree. C. for ten minutes or less.

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