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1. 发明授权

US06986109B2 Practical method for hierarchical-preserving layout optimization of integrated circuit layout 失效
标题翻译：集成电路布局分层维护布局优化的实用方法
公开(公告)号：US06986109B2
公开(公告)日：2006-01-10
申请号：US10438625
申请日：2003-05-15
申请人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
发明人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
摘要翻译：本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。这些变量被约束为整数。本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。这产生了简化的布局方程和简化的目标函数。这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

2. 发明授权

US06189132B1 Design rule correction system and method 失效
标题翻译：设计规则校正系统及方法
公开(公告)号：US06189132B1
公开(公告)日：2001-02-13
申请号：US09057961
申请日：1998-04-09
申请人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
发明人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.
摘要翻译：呈现了根据多个预定标准修改多个对象的布局的方法。定义了一个目标函数，用于测量布局中对象的位置扰动和分离扰动。使用线性约束在设计规则和用于描述布局对象之间的分离的目标函数方面定义线性系统。解决线性系统以同时消除违反设计规则的情况，并且根据线性系统的解决方案来修改布局中对象的形状和位置，使得布局中的对象的总扰动减小。还提出了用于实现本发明的系统。

3. 发明授权

US07117456B2 Circuit area minimization using scaling 失效
标题翻译：电路面积缩小使用缩放
公开(公告)号：US07117456B2
公开(公告)日：2006-10-03
申请号：US10707287
申请日：2003-12-03
申请人： Michael S. Gray , Kevin W. McCullen , Gustavo E. Tellez , Robert F. Walker
发明人： Michael S. Gray , Kevin W. McCullen , Gustavo E. Tellez , Robert F. Walker
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.
摘要翻译：一种方法，系统和程序产品，其以基本规则和用户意图的形式实现电路设计的区域最小化，同时遵守显式和隐式设计约束。最长路径算法用于生成比例因子。缩放因子用于将电路设计的尺寸减小到最小法律尺寸。缩放可能之后是应用minpert分析来校正由缩放引入的任何错误。所产生的设计缩小（或扩展），所有元素都通过相同的因素一起缩减（或增长），并保持元素的相对关系。此外，本发明在存在正循环的情况下是可操作的，可以用缩放来运行，其结冰或冻结规则的尺寸，并且可以应用于技术迁移。

4. 发明授权

US06904575B2 Method for improving chip yields in the presence of via flaring 失效
标题翻译：在存在通孔燃烧的情况下提高芯片产量的方法
公开(公告)号：US06904575B2
公开(公告)日：2005-06-07
申请号：US10064098
申请日：2002-06-11
申请人： Robert J. Allen , Gustavo E. Tellez
发明人： Robert J. Allen , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.
摘要翻译：本发明提供了一种修改过程，该过程减少了集成电路由于通路短路而产生的错误，同时避免了布局设计的不明显，从而允许LVS测试工具对布局设计的验证。本发明鉴定潜在短路通孔是否具有电冗余路径，如果是，则产生原始单元的克隆单元，但没有潜在的短路通孔。克隆的细胞与原始细胞电可比较。此外，当存在电冗余时，形状数据库中的原始单元的每个实例化被克隆单元替换。此外，取决于设计要求，可以将去除的通路的数量最小化或最大化，同时全部通过电气短路被去除。

5. 发明授权

US06941528B2 Use of a layout-optimization tool to increase the yield and reliability of VLSI designs 失效
标题翻译：使用布局优化工具来提高VLSI设计的产出和可靠性
公开(公告)号：US06941528B2
公开(公告)日：2005-09-06
申请号：US10604962
申请日：2003-08-28
申请人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.
摘要翻译：本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。然后，本发明在目标通孔上或附近绘制标记物形状。标记形状仅在每个目标通孔的水平或垂直方向绘制。本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。在扩展期间，不同的标记形状将被扩展到不同的长度。本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。

6. 发明授权

US07961932B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

7. 发明授权

US07289659B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

8. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

9. 发明授权

US07895545B2 Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning 有权
标题翻译：设计子集，特征分析和产量学习的先验设计方法
公开(公告)号：US07895545B2
公开(公告)日：2011-02-22
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

10. 发明授权

US07725864B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07725864B2
公开(公告)日：2010-05-25
申请号：US11854000
申请日：2007-09-12
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

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