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1. 发明授权

US06189132B1 Design rule correction system and method 失效
标题翻译：设计规则校正系统及方法
公开(公告)号：US06189132B1
公开(公告)日：2001-02-13
申请号：US09057961
申请日：1998-04-09
申请人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
发明人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.
摘要翻译：呈现了根据多个预定标准修改多个对象的布局的方法。定义了一个目标函数，用于测量布局中对象的位置扰动和分离扰动。使用线性约束在设计规则和用于描述布局对象之间的分离的目标函数方面定义线性系统。解决线性系统以同时消除违反设计规则的情况，并且根据线性系统的解决方案来修改布局中对象的形状和位置，使得布局中的对象的总扰动减小。还提出了用于实现本发明的系统。

2. 发明授权

US06986109B2 Practical method for hierarchical-preserving layout optimization of integrated circuit layout 失效
标题翻译：集成电路布局分层维护布局优化的实用方法
公开(公告)号：US06986109B2
公开(公告)日：2006-01-10
申请号：US10438625
申请日：2003-05-15
申请人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
发明人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
摘要翻译：本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。这些变量被约束为整数。本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。这产生了简化的布局方程和简化的目标函数。这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

3. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

4. 发明授权

US07895545B2 Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning 有权
标题翻译：设计子集，特征分析和产量学习的先验设计方法
公开(公告)号：US07895545B2
公开(公告)日：2011-02-22
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

5. 发明授权

US07725864B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07725864B2
公开(公告)日：2010-05-25
申请号：US11854000
申请日：2007-09-12
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

6. 发明授权

US06738954B1 Method for prediction random defect yields of integrated circuits with accuracy and computation time controls 有权
标题翻译：用于精确计算时间控制的集成电路预测随机缺陷产量的方法
公开(公告)号：US06738954B1
公开(公告)日：2004-05-18
申请号：US09636478
申请日：2000-08-10
申请人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
发明人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G01R31/31705
摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.
摘要翻译：一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量，每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

7. 发明申请

US20110126163A1 METHOD TO REDUCE DELAY VARIATION BY SENSITIVITY CANCELLATION 失效
标题翻译：通过灵敏度消除来减少延迟变化的方法
公开(公告)号：US20110126163A1
公开(公告)日：2011-05-26
申请号：US12625139
申请日：2009-11-24
申请人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
发明人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
摘要翻译：一种方法接收初始电路设计。该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化，以产生改变的电路设计。

8. 发明授权

US07657859B2 Method for IC wiring yield optimization, including wire widening during and after routing 失效
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US07657859B2
公开(公告)日：2010-02-02
申请号：US11275076
申请日：2005-12-08
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

9. 发明授权

US07337415B2 Systematic yield in semiconductor manufacture 有权
标题翻译：半导体制造系统产量
公开(公告)号：US07337415B2
公开(公告)日：2008-02-26
申请号：US10711978
申请日：2004-10-18
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

10. 发明授权

US07076749B2 Method and system for improving integrated circuit manufacturing productivity 失效
标题翻译：提高集成电路制造生产率的方法和系统
公开(公告)号：US07076749B2
公开(公告)日：2006-07-11
申请号：US10709807
申请日：2004-05-28
申请人： Douglas W. Kemerer , Daniel N. Maynard , Gustavo E. Tellez , Lijiang L. Wang , Peter S. Wissell
发明人： Douglas W. Kemerer , Daniel N. Maynard , Gustavo E. Tellez , Lijiang L. Wang , Peter S. Wissell
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).
摘要翻译：一种用于提高集成电路的制造生产率的方法和系统。该方法包括：（a）生成一组物理设计规则，（b）将规则评分方程分配给所述一组物理设计规则的每个物理设计规则; （c）检查集成电路的物理设计以偏离每个设计规则; （d）使用分配给每个物理设计规则的相应规则评分方程计算每个物理设计规则的分数，在步骤（c）中发现一个或多个偏差; 以及（e）基于步骤（d）中计算出的分数计算集成电路设计的生产率得分。

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