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1. 发明授权

US06986109B2 Practical method for hierarchical-preserving layout optimization of integrated circuit layout 失效
标题翻译：集成电路布局分层维护布局优化的实用方法
公开(公告)号：US06986109B2
公开(公告)日：2006-01-10
申请号：US10438625
申请日：2003-05-15
申请人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
发明人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
摘要翻译：本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。这些变量被约束为整数。本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。这产生了简化的布局方程和简化的目标函数。这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

2. 发明授权

US07761821B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07761821B2
公开(公告)日：2010-07-20
申请号：US11837732
申请日：2007-08-13
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

3. 发明授权

US07302651B2 Technology migration for integrated circuits with radical design restrictions 有权
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07302651B2
公开(公告)日：2007-11-27
申请号：US10904225
申请日：2004-10-29
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50 , G03F1/00 , G03C5/00 , G01R31/26
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

4. 发明授权

US07257783B2 Technology migration for integrated circuits with radical design restrictions 有权
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07257783B2
公开(公告)日：2007-08-14
申请号：US10905008
申请日：2004-12-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

5. 发明授权

US08464189B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US08464189B2
公开(公告)日：2013-06-11
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

6. 发明申请

US20100185997A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20100185997A1
公开(公告)日：2010-07-22
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

7. 发明授权

US07610565B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07610565B2
公开(公告)日：2009-10-27
申请号：US11697798
申请日：2007-04-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

8. 发明授权

US07484197B2 Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs 失效
标题翻译：最小布局扰动为基础的艺术品合法化与层次设计的网格约束
公开(公告)号：US07484197B2
公开(公告)日：2009-01-27
申请号：US11279758
申请日：2006-04-14
申请人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译：一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置使用线性规划解决方案的结果的至少一个小区。

9. 发明授权

US06941528B2 Use of a layout-optimization tool to increase the yield and reliability of VLSI designs 失效
标题翻译：使用布局优化工具来提高VLSI设计的产出和可靠性
公开(公告)号：US06941528B2
公开(公告)日：2005-09-06
申请号：US10604962
申请日：2003-08-28
申请人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.
摘要翻译：本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。然后，本发明在目标通孔上或附近绘制标记物形状。标记形状仅在每个目标通孔的水平或垂直方向绘制。本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。在扩展期间，不同的标记形状将被扩展到不同的长度。本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。

10. 发明授权

US07961932B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

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