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1. 发明授权

US07895545B2 Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning 有权
标题翻译：设计子集，特征分析和产量学习的先验设计方法
公开(公告)号：US07895545B2
公开(公告)日：2011-02-22
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

2. 发明申请

US20090259983A1 METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING 有权
标题翻译：设计产品芯片的设计方法，设计分析，特征分析和理论学习
公开(公告)号：US20090259983A1
公开(公告)日：2009-10-15
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

3. 发明授权

US07657859B2 Method for IC wiring yield optimization, including wire widening during and after routing 失效
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US07657859B2
公开(公告)日：2010-02-02
申请号：US11275076
申请日：2005-12-08
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

4. 发明申请

US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING 有权
标题翻译： IC接线优化方法，包括在路由和之后的线路宽带化
公开(公告)号：US20100023913A1
公开(公告)日：2010-01-28
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

5. 发明授权

US08230378B2 Method for IC wiring yield optimization, including wire widening during and after routing 有权
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US08230378B2
公开(公告)日：2012-07-24
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

6. 发明授权

US07961932B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

7. 发明授权

US07289659B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

8. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

9. 发明授权

US07725864B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07725864B2
公开(公告)日：2010-05-25
申请号：US11854000
申请日：2007-09-12
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

10. 发明授权

US06738954B1 Method for prediction random defect yields of integrated circuits with accuracy and computation time controls 有权
标题翻译：用于精确计算时间控制的集成电路预测随机缺陷产量的方法
公开(公告)号：US06738954B1
公开(公告)日：2004-05-18
申请号：US09636478
申请日：2000-08-10
申请人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
发明人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G01R31/31705
摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.
摘要翻译：一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量，每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

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