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1. 发明申请

US20060226412A1 Thick semi-insulating or insulating epitaxial gallium nitride layers and devices incorporating same 有权
标题翻译：厚半绝缘或绝缘外延氮化镓层和结合其的器件
公开(公告)号：US20060226412A1
公开(公告)日：2006-10-12
申请号：US11103117
申请日：2005-04-11
申请人： Adam Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Smith , Scott Sheppard
发明人： Adam Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Smith , Scott Sheppard
IPC分类号： H01L29/06
CPC分类号： H01L21/0254 , H01L21/0237 , H01L21/02425 , H01L21/02439 , H01L21/02491 , H01L21/02581 , H01L21/0262 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/41766 , H01L29/66462 , H01L29/7787
摘要： Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.
摘要翻译：提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。半绝缘或绝缘GaN外延层具有至少约4μm的厚度。还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

2. 发明申请

US20060208280A1 Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions 有权
标题翻译：能耐受高温反向偏压测试条件的III类氮化物场效应晶体管（FETS）
公开(公告)号：US20060208280A1
公开(公告)日：2006-09-21
申请号：US11080905
申请日：2005-03-15
申请人： Richard Smith , Scott Sheppard , Adam Saxler , Yifeng Wu
发明人： Richard Smith , Scott Sheppard , Adam Saxler , Yifeng Wu
IPC分类号： H01L29/739
CPC分类号： H01L27/0605 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/7787
摘要： Group III Nitride based field effect transistor (FETS) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about 56 volts, a gate to source voltage (Vgs) of from about −8 to about −14 volts and a temperature of about 140 ° C. for at least about 10 hours.
摘要翻译：提供基于III族氮化物的场效应晶体管（FETS），其在约56伏的漏极 - 源极电压（V SUB DS）下操作时具有小于约3.0dB的功率劣化，栅极至约-14伏特的电源电压（V S）和约140℃的温度至少约10小时。

3. 发明申请

US20060255364A1 Heterojunction transistors including energy barriers and related methods 有权
标题翻译：异质结晶体管包括能量屏障和相关方法
公开(公告)号：US20060255364A1
公开(公告)日：2006-11-16
申请号：US11357752
申请日：2006-02-17
申请人： Adam Saxler , Yifeng Wu , Primit Parikh
发明人： Adam Saxler , Yifeng Wu , Primit Parikh
IPC分类号： H01L31/00
CPC分类号： H01L29/7785 , H01L29/2003 , H01L29/207 , H01L29/66462 , H01L29/7783 , H01L29/802
摘要： A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.
摘要翻译：异质结晶体管可以包括包含III族氮化物的沟道层，在沟道层上包含III族氮化物的势垒层，以及包括在沟道层上包含铟的III族氮化物层的能量势垒，使得沟道层在阻挡层和能量屏障之间。阻挡层可以具有大于沟道层的带隙的带隙，并且能量势垒中的铟（In）的浓度可以大于沟道层中的铟（In）的浓度。还讨论了相关方法。

4. 发明申请

US20060118809A1 High power density and/or linearity transistors 有权
标题翻译：高功率密度和/或线性晶体管
公开(公告)号：US20060118809A1
公开(公告)日：2006-06-08
申请号：US11005107
申请日：2004-12-06
申请人： Primit Parikh , Yifeng Wu , Adam Saxler
发明人： Primit Parikh , Yifeng Wu , Adam Saxler
IPC分类号： H01L29/24 , H01L33/00
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/7787
摘要： Field effect transistors having a power density of greater than 25 W/mm when operated at a frequency of at least 4 GHz are provided. The power density may be at least 30 W/mm when operated at 4 GHz. The power density of at least 30 W/mm may be provided at a drain voltage of 120 V. Transistors with a power density of at least 30 W/mm when operated at 8 GHz are also provided. The power density of at least 30 W/mm may be provided at a drain voltage of 120 V. Field effect transistors having a power density of greater than 20 W/mm when operated at a frequency of at least 10 GHz are also provided. Field effect transistors having a power density of at least 2.5 W/mm and a two tone linearity of at least −30 dBc of third order intermodulation distortion at a center frequency of at least 4 GHz and a power added efficiency (PAE) of at least 40% are also provided.
摘要翻译：提供了以至少4GHz的频率工作时功率密度大于25W / mm的场效应晶体管。在4 GHz工作时，功率密度可以至少为30 W / mm。在120V的漏极电压下可以提供至少30W / mm的功率密度。还提供了在8GHz下工作时功率密度至少为30W / mm的晶体管。至少30W / mm的功率密度可以在120V的漏极电压下提供。还提供了在至少10GHz的频率下工作时功率密度大于20W / mm的场效应晶体管。具有至少2.5W / mm的功率密度和至少为4GHz的中心频率的三阶互调失真至少为-30dBc的两个音调线性的场效应晶体管和至少为4GHz的功率增加效率（PAE）也提供了40％。

5. 发明申请

US20060118823A1 Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies 有权
标题翻译：在毫米波频率下具有多瓦输出功率的场效应晶体管（FET）
公开(公告)号：US20060118823A1
公开(公告)日：2006-06-08
申请号：US11005423
申请日：2004-12-06
申请人： Primit Parikh , Yifeng Wu , Adam Saxler
发明人： Primit Parikh , Yifeng Wu , Adam Saxler
IPC分类号： H01L31/072
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/2003 , H01L29/41725
摘要： High electron mobility transistors (HEMT) are provided having an output power of greater than 3.0 Watts when operated at a frequency of at least 30 GHz. The HEMT has a power added efficiency (PAE) of at least about 20 percent and/or a gain of at least about 7.5 dB. The total width of the HEMT is less than about 6.0 mm.
摘要翻译：提供高电子迁移率晶体管（HEMT），其在至少30GHz的频率下工作时具有大于3.0瓦特的输出功率。 HEMT具有至少约20％的功率附加效率（PAE）和/或至少约7.5dB的增益。 HEMT的总宽度小于约6.0mm。

6. 发明申请

US20060202272A1 Wide bandgap transistors with gate-source field plates 审中-公开
标题翻译：具有栅源场的宽带隙晶体管
公开(公告)号：US20060202272A1
公开(公告)日：2006-09-14
申请号：US11078265
申请日：2005-03-11
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Scott Sheppard
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Scott Sheppard
IPC分类号： H01L29/739
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/404 , H01L29/7787
摘要： A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A spacer layer is on at least part of the surface of the plurality of active region between the gate and the drain electrode and between the gate and the source electrode. A field plate is on the spacer layer and extends on the spacer and over the active region toward the drain electrode. The field plate also extends on the spacer layer over the active region and toward the source electrode. At least one conductive path electrically connects the field plate to the source electrode or the gate.
摘要翻译：一种晶体管，包括具有沟道层的有源区，源极和漏极形成为与有源区接触，栅极形成在源极和漏极之间并与有源区接触。间隔层位于栅极和漏电极之间以及栅极和源极之间的多个有源区的表面的至少一部分上。场板位于间隔层上并且在间隔物上延伸并且在有源区上方朝向漏电极延伸。场板还在有源区上的间隔层上延伸并且朝向源电极延伸。至少一个导电路径将场板电连接到源电极或栅极。

7. 发明授权

US09419124B2 Insulating gate AlGaN/GaN HEMT 有权
公开(公告)号：US09419124B2
公开(公告)日：2016-08-16
申请号：US11356791
申请日：2006-02-17
申请人： Primit Parikh , Umesh Mishra , Yifeng Wu
发明人： Primit Parikh , Umesh Mishra , Yifeng Wu
IPC分类号： H01L31/0328 , H01L31/0336 , H01L29/778 , H01L29/51 , H01L23/29 , H01L23/31 , H01L29/20 , H01L29/43
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

8. 发明授权

US09397173B2 Wide bandgap transistor devices with field plates 有权
公开(公告)号：US09397173B2
公开(公告)日：2016-07-19
申请号：US13355766
申请日：2012-01-23
申请人： Primit Parikh , Yifeng Wu
发明人： Primit Parikh , Yifeng Wu
IPC分类号： H01L29/778 , H01L29/40 , H01L29/423 , H01L29/812 , H01L29/16 , H01L29/20
CPC分类号： H01L29/402 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/7787 , H01L29/812
摘要： A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.

9. 发明授权

US09240473B2 High temperature performance capable gallium nitride transistor 有权
标题翻译：耐高温性能的氮化镓晶体管
公开(公告)号：US09240473B2
公开(公告)日：2016-01-19
申请号：US13480328
申请日：2012-05-24
申请人： Sten Heikman , Yifeng Wu
发明人： Sten Heikman , Yifeng Wu
IPC分类号： H01L31/072 , H01L29/778 , H01L29/40 , H01L29/47 , H01L29/66 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/475 , H01L29/66462
摘要： A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.
摘要翻译：在高温下能够高性能的晶体管器件。晶体管包括具有接触有源区的接触层的栅极。当与特定的半导体系统（例如III族氮化物）结合使用时，栅极接触层由具有高肖特基势垒的材料制成，并且在高温下操作时表现出降低的降解。该装置还可以包括场板以进一步增加装置的工作寿命。

10. 发明申请

US20140015066A1 SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS 有权
标题翻译：具有集成电流限制的半导体电子元件
公开(公告)号：US20140015066A1
公开(公告)日：2014-01-16
申请号：US13550445
申请日：2012-07-16
申请人： Yifeng Wu , Umesh Mishra , Srabanti Chowdhury
发明人： Yifeng Wu , Umesh Mishra , Srabanti Chowdhury
IPC分类号： H01L27/088
CPC分类号： H01L27/0883 , H01L27/0605 , H01L29/16 , H01L29/2003 , H01L29/778 , H03K17/687
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.
摘要翻译：电子部件包括高电压耗尽型晶体管和低电压增强型晶体管。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的栅电极电耦合到低电压增强型晶体管。增强型晶体管的导通电阻小于耗尽型晶体管的导通电阻，并且增强型晶体管的最大电流电平小于耗尽型晶体管的最大电流电平。

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