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1. 发明申请

US20060035457A1 Interconnection capacitance reduction 审中-公开
标题翻译：互连电容降低
公开(公告)号：US20060035457A1
公开(公告)日：2006-02-16
申请号：US10915166
申请日：2004-08-10
申请人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.
摘要翻译：对集成电路的制造方法的改进。移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

2. 发明授权

US5994211A Method and composition for reducing gate oxide damage during RF sputter clean 失效
标题翻译：用于在RF溅射清洗期间减少栅极氧化物损伤的方法和组合物
公开(公告)号：US5994211A
公开(公告)日：1999-11-30
申请号：US976033
申请日：1997-11-21
申请人： Zhihai Wang , Wei-Jen Hsia , Wilbur Catabay
发明人： Zhihai Wang , Wei-Jen Hsia , Wilbur Catabay
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/70
CPC分类号： H01L21/02071 , H01L21/76814 , H01L21/76843 , H01L21/76844
摘要： Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
摘要翻译：提供了用于RF溅射清洗接触孔和通孔的方法和组合物，其在孔中提供基本上均匀的电荷分布并使电子阴影最小化。这通过诸如PVD的各向同性地沉积在围绕孔的晶片表面和孔的侧面的导电材料层来实现。各向同性沉积使得在高纵横比下，沟槽和孔沉积在顶部最重，底部最小（由于沉积阴影效应）。沉积的导电材料优选是在沉积插塞材料之前也用作孔中的衬垫的金属。导电材料提供用于负电荷的路径，否则在RF溅射清洗期间积聚在孔的顶部以到达孔的底部，从而防止在孔内和周围累积一种极性的电荷。因此，如上所述，通过常规RF溅射引起的栅极氧化物上的应力得以缓解。

3. 发明授权

US06204550B1 Method and composition for reducing gate oxide damage during RF sputter clean 有权
标题翻译：用于在RF溅射清洗期间减少栅极氧化物损伤的方法和组合物
公开(公告)号：US06204550B1
公开(公告)日：2001-03-20
申请号：US09251702
申请日：1999-02-17
申请人： Zhihai Wang , Wei-Jen Hsia , Wilbur Catabay
发明人： Zhihai Wang , Wei-Jen Hsia , Wilbur Catabay
IPC分类号： H01L23495
CPC分类号： H01L21/02071 , H01L21/76814 , H01L21/76843 , H01L21/76844
摘要： Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
摘要翻译：提供了用于RF溅射清洗接触孔和通孔的方法和组合物，其在孔中提供基本上均匀的电荷分布并使电子阴影最小化。这通过诸如PVD的各向同性地沉积在围绕孔的晶片表面和孔的侧面的导电材料层来实现。各向同性沉积使得在高纵横比下，沟槽和孔沉积在顶部最重，底部最小（由于沉积阴影效应）。沉积的导电材料优选是在沉积插塞材料之前也用作孔中的衬垫的金属。导电材料提供用于负电荷的路径，否则在RF溅射清洗期间积聚在孔的顶部以到达孔的底部，从而防止在孔内和周围累积一个极性的电荷。因此，如上所述，通过常规RF溅射引起的栅极氧化物上的应力得以缓解。

4. 发明申请

US20060035455A1 Interconnect dielectric tuning 失效
公开(公告)号：US20060035455A1
公开(公告)日：2006-02-16
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

5. 发明申请

US20080308937A1 COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATION AND USE THEREOF 审中-公开
标题翻译：无铜半导体器件接口及其制造及其使用方法
公开(公告)号：US20080308937A1
公开(公告)日：2008-12-18
申请号：US12138595
申请日：2008-06-13
申请人： Wilbur Catabay , Julian Searle , Wei-Jen Hsia , Milan Prejda , Rohini Ranganathan , Lahcene Smati , Majid Milani
发明人： Wilbur Catabay , Julian Searle , Wei-Jen Hsia , Milan Prejda , Rohini Ranganathan , Lahcene Smati , Majid Milani
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L23/53223 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.
摘要翻译：本文提供了无铜半导体器件界面的实施例以及用于形成和/或利用其的方法。在一些实施例中，半导体结构可以包括具有暴露的含铜特征的衬底; 以及设置在衬底上方的无铜界面，并且在含铜特征和无铜界面的上表面之间提供导电互连，以便于将衬底电耦合到半导体器件，同时将半导体器件与含铜功能。

6. 发明申请

US20070163993A1 Planarization with reduced dishing 审中-公开
公开(公告)号：US20070163993A1
公开(公告)日：2007-07-19
申请号：US11695169
申请日：2007-04-02
申请人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
发明人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
IPC分类号： C23F1/00 , B44C1/22 , C03C15/00
CPC分类号： B23H5/08 , C23F1/02 , C23F4/00 , C25F3/02 , H01L21/02063 , H01L21/32115 , H01L21/3212 , H01L21/32136 , H01L21/7684
摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

7. 发明申请

US20060118523A1 Planarization with reduced dishing 有权
标题翻译：平面化减少凹陷
公开(公告)号：US20060118523A1
公开(公告)日：2006-06-08
申请号：US11337460
申请日：2006-01-23
申请人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
发明人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
IPC分类号： B44C1/22 , C23F1/00 , C03C15/00
CPC分类号： B23H5/08 , C23F1/02 , C23F4/00 , C25F3/02 , H01L21/02063 , H01L21/32115 , H01L21/3212 , H01L21/32136 , H01L21/7684
摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.
摘要翻译：在衬底上形成平坦化层的方法，其中衬底被清洁，并且形成具有高部分和低部分的表面的层。电阻掩模形成在层的低部分上，但不在层的高部分之上。蚀刻层的表面，其中层的高部分暴露于蚀刻，但是电阻掩模下面的层的低部分不暴露于蚀刻。层的表面的蚀刻继续进行直到层的高部分与层的低部分基本相同的水平，从而提供层的表面的初始平坦化。电阻掩模从层的表面去除，并且层的所有表面被平坦化以提供平坦化层。

8. 发明申请

US20060205203A1 Dual layer barrier film techniques to prevent resist poisoning 有权
公开(公告)号：US20060205203A1
公开(公告)日：2006-09-14
申请号：US11418873
申请日：2006-05-04
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur Catabay
IPC分类号： H01L21/4763 , H01L21/311 , H01L21/31
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

9. 发明申请

US20060166496A1 Incorporating dopants to enhance the dielectric properties of metal silicates 有权
公开(公告)号：US20060166496A1
公开(公告)日：2006-07-27
申请号：US11389643
申请日：2006-03-23
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

10. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

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