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1. 发明申请

US20060035457A1 Interconnection capacitance reduction 审中-公开
标题翻译：互连电容降低
公开(公告)号：US20060035457A1
公开(公告)日：2006-02-16
申请号：US10915166
申请日：2004-08-10
申请人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.
摘要翻译：对集成电路的制造方法的改进。移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

2. 发明申请

US20050208758A1 Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures 有权
标题翻译：用作半导体沟槽和通孔结构中的铜阻挡层的介电阻挡膜
公开(公告)号：US20050208758A1
公开(公告)日：2005-09-22
申请号：US11131003
申请日：2005-05-16
申请人： Hong-Qiang Lu , Peter Burke , Wilbur Catabay
发明人： Hong-Qiang Lu , Peter Burke , Wilbur Catabay
IPC分类号： H01L21/312 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L21/02211 , H01L21/02126 , H01L21/02167 , H01L21/02315 , H01L21/02348 , H01L21/02351 , H01L21/3121 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
摘要翻译：本发明涉及改进的介电铜阻挡层和相关互连结构。一种结构包括具有铜线的半导体衬底。在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。在绝缘层中形成开口以露出铜线的一部分。绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。形成铜塞以填充开口并与下面的铜互连结构电接触。本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

3. 发明申请

US20050176216A1 Ultra low dielectric constant thin film 审中-公开
公开(公告)号：US20050176216A1
公开(公告)日：2005-08-11
申请号：US11106307
申请日：2005-04-14
申请人： Hao Cui , Peter Burke , Wilbur Catabay
发明人： Hao Cui , Peter Burke , Wilbur Catabay
IPC分类号： C23C16/32 , H01L21/00 , H01L21/314 , H01L21/46 , H01L21/768 , H01L29/15
CPC分类号： H01L21/02167 , C23C16/325 , H01L21/022 , H01L21/02274 , H01L21/3148 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76828
摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

4. 发明申请

US20070190784A1 DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 失效
标题翻译：用于增加铜互连结构中电磁寿命的电介质障碍层
公开(公告)号：US20070190784A1
公开(公告)日：2007-08-16
申请号：US11736402
申请日：2007-04-17
申请人： Hao Cui , Peter Burke , Wilbur Catabay
发明人： Hao Cui , Peter Burke , Wilbur Catabay
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

5. 发明申请

US20060237799A1 Carbon nanotube memory cells having flat bottom electrode contact surface 审中-公开
标题翻译：具有平坦的底部电极接触表面的碳纳米管存储单元
公开(公告)号：US20060237799A1
公开(公告)日：2006-10-26
申请号：US11112768
申请日：2005-04-21
申请人： Hongquiang Lu , Peter Burke , Wilbur Catabay
发明人： Hongquiang Lu , Peter Burke , Wilbur Catabay
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： G11C23/00 , B82Y10/00 , G11C13/025 , H01L51/0048 , H01L51/0052
摘要： The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.
摘要翻译：本发明涉及制造具有基本平坦的接触表面的底部电极的纳米管机电存储单元的结构和方法。底部电极被配置为使得在存储器单元的操作期间，电池的纳米管横截面可以与底部电极的基本平坦的表面接触。

6. 发明申请

US20050090036A1 ULTRA LOW DIELECTRIC CONSTANT THIN FILM 失效
标题翻译：超低介电常数薄膜
公开(公告)号：US20050090036A1
公开(公告)日：2005-04-28
申请号：US10691400
申请日：2003-10-22
申请人： Hao Cui , Peter Burke , Wilbur Catabay
发明人： Hao Cui , Peter Burke , Wilbur Catabay
IPC分类号： C23C16/32 , H01L21/00 , H01L21/314 , H01L21/46 , H01L21/768 , H01L29/15
CPC分类号： H01L21/02167 , C23C16/325 , H01L21/022 , H01L21/02274 , H01L21/3148 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76828
摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.
摘要翻译：在基底上形成基本上无氧的碳化硅层的方法，其中碳化硅层的介电常数小于约4。基板保持在约零摄氏度和约百摄氏度之间的沉积温度，并且以不超过约一千科学立方厘米每分钟的速率引入四甲基硅烷的气流。沉积压力保持在约1毫乇至约100乇之间，并且以不大于约2千瓦的功率产生射频等离子体放电。当形成所需的碳化硅层厚度时，等离子体放电停止。

7. 发明申请

US20060281256A1 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US20060281256A1
公开(公告)日：2006-12-14
申请号：US11312849
申请日：2005-12-20
申请人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

8. 发明申请

US20060278902A1 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US20060278902A1
公开(公告)日：2006-12-14
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
发明人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

9. 发明授权

US08434394B1 Apparatus for adapting a rocket-assisted projectile for launch from a smooth bore tube 有权
标题翻译：用于使火箭辅助的弹丸用于从光滑的钻孔管发射的装置
公开(公告)号：US08434394B1
公开(公告)日：2013-05-07
申请号：US12580412
申请日：2009-10-16
申请人： Gregory Malejko , Daniel Pascua , Peter Burke , Keith Fulton
发明人： Gregory Malejko , Daniel Pascua , Peter Burke , Keith Fulton
IPC分类号： F41F3/00 , F42B15/00
CPC分类号： F42B14/06 , F42B10/14 , F42B15/105 , F42B15/36
摘要： An apparatus for adapting a rocket-assisted artillery projectile of a first caliber for firing from a smooth bore tube of a second caliber may include an adapter for connecting to an aft end of the rocket-assisted artillery projectile. The adapter may include a main channel for receiving rocket exhaust, a plurality of sub-channels that lead from the main channel to an exterior of the adapter, and an ignition channel that leads from the main channel to an ignition delay disposed in the adapter. A tail boom may be fixed to an aft end of the adapter. The tail boom may include an opening in a fore end that communicates with the ignition delay in the adapter. Lifting surfaces, such as fins, may be attached to the tail boom.
摘要翻译：用于使来自第二口径的光滑钻孔管的第一口径的火箭辅助炮弹的适配装置可以包括用于连接到火箭辅助炮弹的后端的适配器。适配器可以包括用于接收火箭排气的主通道，从主通道引导到适配器的外部的多个子通道以及从主通道引导到设置在适配器中的点火延迟的点火通道。尾杆可以固定到适配器的后端。尾杆可以包括与适配器中的点火延迟相通的前端开口。提升表面，例如翅片，可附接到尾部吊杆。

10. 发明申请

US20070272058A1 Direct Smelting Plant and Process 有权
标题翻译：直接冶炼厂和工艺
公开(公告)号：US20070272058A1
公开(公告)日：2007-11-29
申请号：US10576852
申请日：2004-10-16
申请人： Andreas Orth , David Leigh , Peter Burke
发明人： Andreas Orth , David Leigh , Peter Burke
IPC分类号： C21B15/00 , C22B3/02
CPC分类号： F27B3/18 , C21B5/023 , C21B13/00 , C21B13/0013 , C21B13/143 , C21C5/567 , F27D13/00 , Y02P10/216
摘要： The present invention relates to a direct smelting plant and a direct smelting process for producing molten metal from a metalliferous feed material, such as ores, partly reduced ores, and metal-containing waste streams, the latter of which comprising the steps of (a) pretreating metalliferous feed material in a pretreatment unit and producing pretreated feed material having a temperature of at least 200° C., (b) storing pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material storage means, (c) transferring pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material transfer line to a solids delivery means of a direct smelting vessel, and (d) delivering pretreated metalliferous feed material into the direct smelting vessel and smelting metalliferous feed material to molten metal in the vessel.
摘要翻译：本发明涉及一种直接熔炼设备和用于从含金属的原料如矿石，部分还原的矿石和含金属的废物流中生产熔融金属的直接熔炼方法，后者包括以下步骤：（a）在预处理单元中预处理含金属进料，并生产温度至少为200℃的预处理进料;（b）在热进料材料储存器中储存温度至少为200℃的预处理含金属进料是指（c）在热进料输送管线中将压力为至少200℃的预处理的含金属进料传送到直接熔炼容器的固体输送装置，以及（d）将预处理的含金属进料输送到直接熔炼容器和冶炼含金属进料到容器中的熔融金属。

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